公开(公告)号：EP0035322A1

公开(公告)日：1981-09-09

申请号：EP81300376.1

申请日：1981-01-29

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Kusumi, Katsuaki ,  Nakajima, Yoshihiro

IPC分类号： G05B19/18

CPC分类号： G05B19/4147 ,  G05B2219/34196 ,  G05B2219/36373

摘要： There is provided a programmable sequence controller which need not be equipped with a tape reader for reading a paper tape bearing a punched program or the like. A prepared sequence program or the like is punched in a paper tape in accordance with the standards of a paper tape reader 101 a which is provided in a numerical control device 1, and then is transferred from the numerical control device 1 to a random access memory 201c in the programmable sequence controller 2. The sequence program is read from the random access memory 201 c to permit the execution of sequential operations by processing the program.

摘要翻译： 提供了一种可编程顺序控制器，其不需要配备用于读取承载穿孔程序等的纸带的带读取器。 根据数字控制装置1中设置的纸带阅读器101a的标准将准备好的顺序程序等打在纸带上，然后从数字控制装置1传送到随机存取存储器 201c存储在可编程序列控制器2中。从随机存取存储器201c读取序列程序以允许通过处理程序来执行顺序操作。

公开(公告)号：EP0029294A1

公开(公告)日：1981-05-27

申请号：EP80303547.6

申请日：1980-10-09

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Yamazaki, Etsuo ,  Sasaki, Takao ,  Yamaguchi, Masashi

IPC分类号： B23Q35/123

CPC分类号： B23Q35/123

摘要： During a tracing operation of a tracer head (TR) the present position of the tracer head in the Z-axis direction is detected and a maximum value (Zma) of the detected tracer head positions is stored in a memory means (AR). When the tracer head (TR) is returned from a trace terminating end (LX2) to a trace starting end (LX1), it is quickly returned to a position (Zma + a) corresponding to the sum of the stored maximum value (Zma) and a constant value (a).

公开(公告)号：EP0028068A1

公开(公告)日：1981-05-06

申请号：EP80303261.4

申请日：1980-09-17

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Kusumi, Katsuaki ,  Nakajima, Yoshihiro

IPC分类号： G05B19/04

CPC分类号： G05B19/056 ,  G05B2219/13005 ,  G05B2219/13008 ,  G05B2219/13093 ,  Y10T483/10 ,  Y10T483/123

摘要： A sequence controller executes sequence control of a machine tool through a sequence program by executing a subroutine program. A function command specifying a subroutine (ROT SUB 6) is divided into control condition data (RNO, DIR, POS, ACT) and operational parameters (Number of rotational positionings, present position address etc.). A memory holds the control condition data (RNO, DIR, POS, ACT). In response to a command the control condition data is read from the memory to a register. Under control of the subroutine program the control condition data is read from the register and the operational parameters are read. The result of. execution of the subroutine program is stored in the memory and the machine tool is controlled in dependence upon that result.
The subroutine program thus includes command (RD or. RD. STK) for reading the control condition data from the register, and operational parameter data. Sequence control involving the subroutine program can be represented in a sequence diagram in which a function command for the subroutine is divided into control conditions (RNO, DIR, POS, ACT) and parameters (number of rotational positionings present position address etc.).

摘要翻译： 序列控制器通过执行子例程程序通过执行一个顺序程序的机床的顺序控制。 函数命令指定的子程序（RED SUB 6）被划分成控制条件数据（RNO，DIR，POS，ACT）和操作参数（旋转positionings数目，当前位置地址等）。 存储器保持控制条件数据（RNO，DIR，POS，ACT）。 响应于命令的控制条件数据从存储器到寄存器读出。 下的子例程程序的控制的控制条件的数据从寄存器中读出和操作参数被读出。 的子例程程序的执行结果存储在所述存储器和所述机床在该结果时依赖性控制。 ... 子程序程序包括命令THUS（RD或RD。STK），用于从所述寄存器读取的控制状态数据，并且运行参数数据。 顺序控制涉及的子例程程序可在其中用于子程序的功能命令被划分为控制条件（RNO，DIR，POS，ACT）和参数（旋转positionings当前位置地址，数量等）的序列图来表示。

公开(公告)号：EP0026630A1

公开(公告)日：1981-04-08

申请号：EP80303335.6

申请日：1980-09-24

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Sasaki, Takao ,  Yamazaki, Etuo

IPC分类号： G05B19/18 ,  B23Q35/12

CPC分类号： B23Q35/121

摘要： In one forward or backward trace path on a model (MDL), a jerk inatracer control system point (P 1 to P 4 ) in the surface configuration of the model (MDL) is detected and the position of the jerk point is stored in a memory (MEM). The reduction of the trace velocity is started a predetermined distance (a) short of the stored position of the jerk point (P 1 to P 4 ) in the trace direction and when a jerk point is detected again, the position of the jerk point previously stored in the memory (MEM) is updated and the reduction of the trace velocity is released, thus achieving high accuracy trace.

公开(公告)号：EP0023124A3

公开(公告)日：1981-03-25

申请号：EP80302387

申请日：1980-07-16

申请人： Fanuc Ltd

发明人： Imazeki, Ryoji ,  Hattori, Masayuki

IPC分类号： G11C19/08

CPC分类号： G11C19/085 ,  G06F1/26 ,  H02H3/247

摘要： The power source device 3 has a first DC power source circuit 12 for supplying a DC voltage Ec for control circuitry 2 of bubble memory unit 1, a second DC power source circuit 13 for supplying a voltage Ed for drive circuitry of the unit 1, and also supplies a memory enable signal Me for the unit 1. A comparator 14 compares Ec with a reference level Vm. Source circuit 13 is actuated at a given delay time after Ec exceeds Vm whereafter Me is produced. When Ec falls below Vm, Me is cancelled immediately and source circuit 13 is switched off after a time delay.

公开(公告)号：EP0023821A2

公开(公告)日：1981-02-11

申请号：EP80302613.7

申请日：1980-07-31

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Inoue, Michiya

IPC分类号： G11C29/00

CPC分类号： G06F11/1004

摘要： A processor 3 reads the words of a logical block, e.g. BL i , from memory, e.g. RAM2, and checks the block by operating on the words and comparing the result with a predetermined value.
For example, processor 3 performs exclusive OR operations between homologous bits of a word Wi, W 2 , W 3 , W 4 , OCW i , and contents of a register 3c and sets the resultant in register 3c. Initially register 3c holds all «O»s. When first word Wi is «01001010» the resultant set in register 3c is «01001010». Homologous bits of this resultant and second word W 2 are exclusive OR-ed to give «11100000» in register 3c. Similar operations are effected for W 3 , W 4 and OCW i . If block BL i checks correctly a predetermined result «00000000» is found in register 3c.
Word OCW I is an operational control word provided in block BL i , when words W 1 to W 4 are stored, to ensure that the predetermined result will be arrived at in the case of correct checking.

摘要翻译： 处理器3读取的逻辑块的话，E.G. BLi上，从内存，E.G. RAM2，并且检查通过对话操作，并将结果与​​一个预定值进行比较的块。 ... 对于实施例，处理器3个执行排他或字W1，W2，W3，W4，OCWi的同源位之间的操作，以及寄存器3c的内容，并设置得到的寄存器3c中。 最初注册3C保存所有<< O >>页。 当第一个字W1是<< 01001010 >>的结果集寄存器3C是<< 01001010 >>。 这和引发的第二个字W2同源位异或编辑给<< 11100000 >>寄存器3C。 类似的操作，实现了W3，W4和OCWi。 如果块BLi上正确检查预定的结果<< 00000000 >>在寄存器3C找到。 ... 字OCWi是在块BLi上，当字W1到W4被存储提供了一种操作控制字，以确保DA​​SS死预定结果将在正确的检查的情况下得出。

公开(公告)号：EP0014563A3

公开(公告)日：1981-01-07

申请号：EP80300276

申请日：1980-01-30

申请人： Fanuc Ltd

发明人： Imazeki, Ryoji ,  Yamazaki, Etuo ,  Sasaki, Takao

IPC分类号： G05B21/02 ,  B23Q35/12

CPC分类号： B23Q35/121 ,  G05B2219/49392

摘要： Tracer control apparatus, for a tracer machining system, has a memory storing position A, along the PICKFEED AXIS, of the first clamping feed in initial tracing of a clamping feed area H1 and position B at which clamping feed is absent after initial tracing of area H1. Using the stored positions the apparatus causes repeat tracings back and forth between A and B. Clamping level setting means 11 to 15 set an initial clamping level LCZ for clamping feeds in initial tracing of area H1, and add increments inc to that level for successive repeat tracings. Only when the incremented clamping level is not reached in a repeat tracing, or the incremented level reaches a limit value, does tracing proceed beyond area H1. The clamping level is set back to its initial value. A method of machining is provided in which repeat tracing is carried out only in areas where required, e.g. H1, in dependence upon stored positions A and B and incrementing clamping levels.

公开(公告)号：EP0026630B1

公开(公告)日：1984-03-21

申请号：EP80303335.6

申请日：1980-09-24

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Sasaki, Takao ,  Yamazaki, Etuo

IPC分类号： G05B19/18 ,  B23Q35/12

CPC分类号： B23Q35/121

公开(公告)号：EP0016604B1

公开(公告)日：1983-05-18

申请号：EP80300754.1

申请日：1980-03-12

申请人： FANUC LTD.

发明人： Imazeki, Ryoji ,  Yamazaki, Etuo ,  Sasaki, Takao

IPC分类号： G05B19/407

CPC分类号： G05B19/416 ,  G05B2219/43048

公开(公告)号：EP0025651A3

公开(公告)日：1982-06-09

申请号：EP80302914

申请日：1980-08-22

申请人： Fanuc Ltd

发明人： Imazeki, Ryoji ,  Yamazaki, Etuo ,  Sasaki, Takao

IPC分类号： G05B19/407 ,  G06F07/544 ,  G06F15/353

CPC分类号： G05B19/416 ,  G05B2219/43048 ,  G06F7/544

摘要： The converter circuit has n memory elements M1 to Mn. An input signal is fed through terminal IN to the memory elements M1 to Mn. At a timing instant (e.g. t1) element M1 holds the present value (e.g. 4) of the input signal and elements M2 to Mn hold the values (e.g. 0) of the input signal at n-1 preceding timing instants. The values held in the memory elements M1 to Mn are added (in adder ADD), the result divided by n (in divider DV), and the divided result fed at an output signal value from output terminal OUT. Where the input signal is a signal indicating a desired amount of movement, of a movable machine part, in numerical control apparatus, an abrupt change in the input signal is converted to a gradual change in the output signal, which facilitates smooth control of the movable machine part.

摘要翻译： 转换器电路具有n个存储元件M1至Mn。 输入信号通过端子IN馈送到存储元件M1至Mn。 在时刻（例如t1），元件M1保持输入信号的当前值（例如4），元件M2至Mn保持在n-1个先前定时时刻的输入信号的值（例如0）。 保持在存储元件M1至Mn中的值被加到（在加法器ADD中），结果除以n（在分频器DV中），分频结果以输出端OUT输出。 ...其中输入信号是指示可移动机器部件的期望移动量的信号，在数字控制装置中，输入信号的突然变化被转换为输出信号的逐渐变化，这有利于 平稳地控制可动机械部件。