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公开(公告)号：EP1791261A3
公开(公告)日：2007-07-25
申请号：EP07101761.0
申请日：1996-11-18
申请人： Fujitsu Ltd.
CPC分类号： H03L7/23 , H03L7/099 , H03L7/0995 , H03L7/0997 , H04L7/033
摘要： A semiconductor integrated circuit (30) including a unit circuit (20) which constructs at least one part of a phase-locked loop and operates as a clock recovery circuit to generate a synchronized oscillation signal based on input data, and retiming means (30A) which generates recovery data by said oscillation output signal from said input data. The retiming means (30A) comprises:
- a pulse generating circuit (306) detecting a level transition of said input data and generating a detected pulse (306a) having a pulse width δt to be provided to said unit circuit (20);
- a delay circuit (307) delaying said input data by a given delay time determined based on said pulse width δt in order to provide delayed data (307a); and
- a retiming circuit (308) carrying out a retiming operation for said delayed data (307a) by one of a leading edge and a trailing edge of said synchronized oscillation signal (203a) in order to generate said recovery data.-
公开(公告)号：EP1791261A2
公开(公告)日：2007-05-30
申请号：EP07101761.0
申请日：1996-11-18
申请人： Fujitsu Ltd.
CPC分类号： H03L7/23 , H03L7/099 , H03L7/0995 , H03L7/0997 , H04L7/033
摘要： A semiconductor integrated circuit (30) including a unit circuit (20) which constructs at least one part of a phase-locked loop and operates as a clock recovery circuit to generate a synchronized oscillation signal based on input data, and retiming means (30A) which generates recovery data by said oscillation output signal from said input data. The retiming means (30A) comprises:
- a pulse generating circuit (306) detecting a level transition of said input data and generating a detected pulse (306a) having a pulse width δt to be provided to said unit circuit (20);
- a delay circuit (307) delaying said input data by a given delay time determined based on said pulse width δt in order to provide delayed data (307a); and
- a retiming circuit (308) carrying out a retiming operation for said delayed data (307a) by one of a leading edge and a trailing edge of said synchronized oscillation signal (203a) in order to generate said recovery data.摘要翻译： 一种半导体集成电路（30），包括构成锁相环的至少一部分并作为时钟恢复电路工作以产生基于输入数据的同步振荡信号的单元电路（20）和重定时装置（30A） 它通过来自所述输入数据的所述振荡输出信号产生恢复数据。 再定时部件（30A）包括： - 脉冲产生电路（306），用于检测所述输入数据的电平转换并产生具有要提供给所述单元电路（20）的脉冲宽度δt的检测脉冲（306a）; - 延迟电路（307），将所述输入数据延迟基于所述脉冲宽度δt确定的给定延迟时间，以便提供延迟数据（307a）; 以及 - 重定时电路（308），用于通过所述同步振荡信号（203a）的前沿和后沿中的一个对所述延迟数据（307a）执行重定时操作，以便产生所述恢复数据。
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