公开(公告)号：EP0528283A2

公开(公告)日：1993-02-24

申请号：EP92113445.8

申请日：1992-08-06

申请人： SONY CORPORATION

发明人： Chiaki, Takano

IPC分类号： G06F1/04 ,  H03K3/03

CPC分类号： H03L7/0997 ,  G06F1/08 ,  H03K3/0315 ,  H03L7/089 ,  H03L7/183

摘要： A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator (20), a divider (14), a phase comparator (15), and an up-down counter (16). The ring oscillator (20) provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider (14) divides the oscillation frequency from the ring oscillator (20) by a specified number. The phase comparator (15) compares the frequency of the signal from the divider (14) with the frequency of the external clock signal (S fe ). The up-down counter (16) controls the oscillation frequency of the ring oscillator (20) based on the comparison result from the comparator (15). The clock generator is controlled by an external clock signal (S fe ) to generate an Internal clock signal (S fc ) having a higher frequency and outputs both signals. By use of a digital integrated circuit technology alone, it becomes possible to include slow operating semiconductor elments and fast operating semiconductor elements on the same circuit chip without sacrificing the excellent characteristics of the latter.

摘要翻译： 一种具有时钟信号发生器的半导体集成电路，包括环形振荡器（20），分频器（14），相位比较器（15）和升降计数器（16）。 环形振荡器（20）提供由构成振荡器的电路元件提供的延迟时间之和确定的可变振荡频率。 分频器（14）将来自环形振荡器（20）的振荡频率除以指定数量。 相位比较器（15）将来自分频器（14）的信号的频率与外部时钟信号（Sfe）的频率进行比较。 升降计数器（16）根据比较器（15）的比较结果来控制环形振荡器（20）的振荡频率。 时钟发生器由外部时钟信号（Sfe）控制，以产生具有较高频率的内部时钟信号（Sfc）并输出两个信号。 通过单独使用数字集成电路技术，可以在相同的电路芯片上包括缓慢的半导体元件和快速操作的半导体元件，而不会牺牲后者的优异特性。

公开(公告)号：EP1791262A3

公开(公告)日：2007-07-25

申请号：EP07101756.0

申请日：1996-11-18

申请人： FUJITSU LIMITED

发明人： Tamamura, Masaya Fujitsu Limited ,  Ohishi, Syouji Fujitsu Limited

IPC分类号： H03L7/06 ,  H04L7/033 ,  H03L7/23 ,  H03L7/099

CPC分类号： H03L7/23 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/0997 ,  H04L7/033

摘要： A semiconductor integrated circuit (30) including a unit circuit (20) which constructs at least one part of a phase-locked loop and operates as a clock recovery circuit to generate a synchronized oscillation signal based on input data, and retiming means (30A) which generates recovery data by said oscillation output signal from said input data. The unit circuit includes an oscillator (203) generating an oscillation output signal (203a) whose oscillation frequency is changed to substantially M x (m/n) when a transmission rate of the input data (11) is changed to M x (m/n), where M is a given frequency, and m, n are 1, 2, 3....; and a phase comparator (201). The oscillation output signal (203a) generated in the oscillator (203) is provided to the phase comparator (201) without passing through a divider and is directly compared with the input data.

摘要翻译： 一种半导体集成电路（30），包括构成锁相环的至少一部分并作为时钟恢复电路工作以产生基于输入数据的同步振荡信号的单元电路（20）和重定时装置（30A） 它通过来自所述输入数据的所述振荡输出信号产生恢复数据。 该单元电路包括振荡器（203），当输入数据（11）的传输速率改变为M×（m / n）时，该振荡器产生振荡频率被改变为基本上M×（m / n）的振荡输出信号（203a） n），其中M是给定频率，并且m，n是1,2,3 ......; 和相位比较器（201）。 在振荡器（203）中产生的振荡输出信号（203a）在不经过分频器的情况下提供给相位比较器（201），并直接与输入数据进行比较。

公开(公告)号：EP0996998A1

公开(公告)日：2000-05-03

申请号：EP98931699.7

申请日：1998-06-26

申请人： CREDENCE SYSTEMS CORPORATION

发明人： VANDERSCHOOT, Hens, Christopher ,  WASSON, Timothy, M.

IPC分类号： H03H11/26

CPC分类号： H03L7/0805 ,  H03K5/13 ,  H03K5/131 ,  H03L7/0997 ,  H03L7/181

摘要： A system for compensating for thermal drift of an output signal (OUT1) produced by a logic circuit (12) in response to an input CLOCK signal after a temperature dependent delay includes a variable delay circuit (14), an oscillator (26) and a digital phase lock controller (28). The delay circuit (14) delays the OUT1 signal to produce a compensated output signal (OUT2) with a variable delay controlled by input CONTROL data. The oscillator (26) generates an output signal (OSC_OUT) having a period also controlled by the input CONTROL data which is substantially proportional to the sum of the temperature dependent delay of the logic circuit (12) and the delay of the variable delay circuit (14). The digital phase lock controller (28) continually monitors the period of the OSC_OUT signal and adjusts the CONTROL data so that the period of the OSC_OUT signal remains substantially constant. This ensures that the delay between the CLOCK signal and OUT2 remains constant despite temperature dependent variations in the delay of the logic circuit (12).

公开(公告)号：EP0657796A3

公开(公告)日：1998-09-02

申请号：EP94119499

申请日：1994-12-09

申请人： TEXAS INSTRUMENTS DEUTSCHLAND

发明人： ZIEGLER HORST ,  DIEWALD HORST ,  PREXL FRANZ ,  BAYER ERICH

IPC分类号： H03K3/03 ,  G06F1/08 ,  H03K5/135 ,  H03L7/06 ,  H03L7/089 ,  H03L7/099

CPC分类号： G06F1/08 ,  H03K5/135 ,  H03L7/089 ,  H03L7/0995 ,  H03L7/0997

摘要： 1. A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.

公开(公告)号：EP0771075A3

公开(公告)日：1997-12-03

申请号：EP96115538.9

申请日：1996-09-27

申请人： VLSI TECHNOLOGY, INC.

发明人： Nielson, Edward T.

IPC分类号： H03L7/099 ,  H03L7/18

CPC分类号： H03L7/0995 ,  G06F7/605 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03K5/00006 ,  H03L7/0997 ,  H03L7/16 ,  H03L7/18 ,  H03L2207/10

摘要： A phase locked loop (46) including a comparator (50), a VCO controller (52), and a VCO (54) having a multi-stage oscillator portion and a combinational logic portion. The comparator (50) is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller (52) is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency. A method for multiplying an input clock frequency includes the steps of applying an input clock to a delay chain, developing a plurality of phase-shifted clocks by tapping into the delay chain, and combining the plurality of phase-shifted clock in combinational logic to produce an output clock having a frequency that is a multiple of the input clock frequency.

摘要翻译： 包括具有多级振荡器部分和组合逻辑部分的比较器（50），VCO控制器（52）和VCO（54）的锁相环（46）。 比较器（50）响应于输入时钟和VCO比较时钟并且可操作地产生比较器输出信号。 VCO控制器（52）响应于比较器输出信号并且可操作以产生VCO控制信号。 多级振荡器部分被配置为在VCO控制信号的控制下在稳定状态期间以VCO时钟频率振荡，并且还用于在VCO时钟频率下产生多个时钟相位。 组合逻辑部分响应于多个时钟相位中的至少一些，并且可操作地组合时钟相位以创建具有为输入时钟频率的倍数的输出时钟频率的输出时钟。 用于使输入时钟频率相乘的方法包括以下步骤：将输入时钟施加到延迟链，通过点击进入延迟链开发多个相移时钟，以及将多个相移时钟组合在组合逻辑中以产生 输出时钟的频率是输入时钟频率的倍数。

公开(公告)号：EP1791262A2

公开(公告)日：2007-05-30

申请号：EP07101756.0

申请日：1996-11-18

申请人： FUJITSU LIMITED

发明人： Tamamura, Masaya Fujitsu Limited ,  Ohishi, Syouji Fujitsu Limited

IPC分类号： H03L7/099 ,  H03L7/23 ,  H03L7/06 ,  H04L7/033

CPC分类号： H03L7/23 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/0997 ,  H04L7/033

摘要： A semiconductor integrated circuit (30) including a unit circuit (20) which constructs at least one part of a phase-locked loop and operates as a clock recovery circuit to generate a synchronized oscillation signal based on input data, and retiming means (30A) which generates recovery data by said oscillation output signal from said input data. The unit circuit includes an oscillator (203) generating an oscillation output signal (203a) whose oscillation frequency is changed to substantially M x (m/n) when a transmission rate of the input data (11) is changed to M x (m/n), where M is a given frequency, and m, n are 1, 2, 3....; and a phase comparator (201). The oscillation output signal (203a) generated in the oscillator (203) is provided to the phase comparator (201) without passing through a divider and is directly compared with the input data.

摘要翻译： 一种半导体集成电路（30），包括构成锁相环的至少一部分并作为时钟恢复电路的单元电路（20），用于基于输入数据产生同步的振荡信号，以及重新定时装置（30A） 其通过来自所述输入数据的所述振荡输出信号产生恢复数据。 单位电路包括当输入数据（11）的传输速率变为M×（m / n）时产生振荡频率变化为大致M×（m / n）的振荡输出信号（203a）的振荡器（203） n），其中M是给定频率，m，n分别为1,2,3 ...; 和相位比较器（201）。 在振荡器（203）中产生的振荡输出信号（203a）被提供给相位比较器（201）而不通过分频器，并且与输入数据直接比较。

公开(公告)号：EP1406390A1

公开(公告)日：2004-04-07

申请号：EP03078676.8

申请日：1998-01-19

申请人： SANYO ELECTRIC Co., Ltd.

发明人： Kiyose, Masashi c/o Sanyo Electric Co. Ltd. ,  Ito, Hiroya c/o Sanyo Electric Co. Ltd.

IPC分类号： H03L7/089 ,  H03L7/095 ,  H04N9/45 ,  H03L7/10

CPC分类号： H03L7/0997 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/095 ,  H03L7/10 ,  H03L7/107 ,  H04N9/45 ,  H04N11/146

摘要： A phase locked loop (PLL) circuit (70) for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock comprises
   a voltage controlled oscillator (107) receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage;
   a comparison circuit (12) receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result;
   a charge pump circuit (20), connected to said comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the charge pump circuit pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential;
   a low-pass filter (30), connected between said charge pump circuit and said voltage controlled oscillator, for smoothing the output of the charge pump circuit to produce the control voltage;
   a lock detector (72) for receiving the reference clock and the oscillation clock, detecting if the oscillation clock maintains a substantially constant phase difference with respect to the phase of the reference clock and producing a detection signal indicative of a detection result; and
   a switch (71), connected to one of the input and output of said low-pass filter and responsive to the detection signal from said lock detector, the switch operating to supply one of the ground potential and the power supply potential to one of the input and output of said low-pass filter when the oscillation clock does not maintain a substantially constant phase difference with respect to the phase of the reference clock for at least a predetermined time.

摘要翻译： 用于产生相对于参考时钟的相位保持基本上恒定的相位差的振荡时钟的锁相环（PLL）电路（70）包括接收控制电压并产生振荡时钟的振荡时钟的压控振荡器（107） 对应于控制电压的频率; 比较电路（12），接收参考时钟和振荡时钟并将参考时钟和振荡时钟的相位彼此比较以产生指示比较结果的比较信号; 连接到所述比较电路的电荷泵电路（20），接地电位和电源电位，用于接收比较信号，并且响应于比较信号选择接地电位和电源电位中的一个，其中， 当选择接地电位时，电荷泵电路从电荷泵电路的输出端子将恒定电流拉到地，并且当选择电源电位时向电荷泵电路的输出端子提供恒定电流，由此产生输出 交替地重复地电位和电源电位; 低通滤波器（30），连接在所述电荷泵电路和所述压控振荡器之间，用于平滑所述电荷泵电路的输出以产生所述控制电压; 锁定检测器（72），用于接收参考时钟和振荡时钟，检测振荡时钟相对于参考时钟的相位是否保持基本上恒定的相位差，并产生指示检测结果的检测信号; 和连接到所述低通滤波器的输入和输出之一并响应于来自所述锁定检测器的检测信号的开关（71），所述开关操作以将地电位和电源电位中的一个提供给 所述低通滤波器的输入和输出在所述振荡时钟相对于所述参考时钟的相位不保持基本恒定的相位差达至少预定时间时进行。

公开(公告)号：EP1040580A1

公开(公告)日：2000-10-04

申请号：EP99941464.2

申请日：1999-07-19

申请人： Koninklijke Philips Electronics N.V. ,  STMicroelectronics S.A. ,  FRANCE TELECOM

发明人： LABRAM, Steven, M. ,  MARBOUX, Guy

IPC分类号： H03K19/003 ,  H03L7/099 ,  H03K3/03

CPC分类号： H03K3/0315 ,  H03K19/00384 ,  H03L1/00 ,  H03L7/0997

摘要： The invention concerns a circuit whereof the operational speed varies according to temperature, supply voltage and the intrinsic quality of the circuit transistors, associated with a compensating circuit comprising a constant current source (26) supplying a substantially constant current independent of temperature, voltage supply and the intrinsic quality of the circuit transistors, a variable current source (28) supplying a current which increases in inverse proportion with temperature, supply voltage and the intrinsic quality of the circuit transistors, and means for decreasing the circuit operational speed when the difference in the currents produced by the first and second sources increases.

公开(公告)号：EP0771075A2

公开(公告)日：1997-05-02

申请号：EP96115538.9

申请日：1996-09-27

申请人： VLSI TECHNOLOGY, INC.

发明人： Nielson, Edward T.

IPC分类号： H03L7/099 ,  H03L7/18

CPC分类号： H03L7/0995 ,  G06F7/605 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03K5/00006 ,  H03L7/0997 ,  H03L7/16 ,  H03L7/18 ,  H03L2207/10

摘要： A phase locked loop (46) including a comparator (50), a VCO controller (52), and a VCO (54) having a multi-stage oscillator portion and a combinational logic portion. The comparator (50) is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller (52) is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency. A method for multiplying an input clock frequency includes the steps of applying an input clock to a delay chain, developing a plurality of phase-shifted clocks by tapping into the delay chain, and combining the plurality of phase-shifted clock in combinational logic to produce an output clock having a frequency that is a multiple of the input clock frequency.

公开(公告)号：EP0657796A2

公开(公告)日：1995-06-14

申请号：EP94119499.5

申请日：1994-12-09

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Ziegler, Horst ,  Diewald, Horst ,  Prexl, Franz ,  Bayer, Erich

IPC分类号： G06F1/08

CPC分类号： G06F1/08 ,  H03K5/135 ,  H03L7/089 ,  H03L7/0995 ,  H03L7/0997

摘要： 1. A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.

摘要翻译： 1，一种时钟发生器包括一参考振荡器（10），数字关闭延迟链（12），数字分频器（14）和一个数字相位比较器（16）。 分频器（14）被连接在可调节的延迟链（12）和相位比较器（16）的一个输入端的输出端之间。 参考振荡器（10）的输出端连接到相位比较器（16）的另一个输入端。 相位比较器的输出（16）和所述延迟链（12）连接的数字递增 - 递减计数器（18），所有这是确定性的由相位比较器（16）的输出信号开采的计数方向，并通过装置之间 其中延迟链（12）的相应的长度的是可调节的。