公开(公告)号：EP1557019A4

公开(公告)日：2006-06-07

申请号：EP03779213

申请日：2003-10-23

申请人： GCT SEMICONDUCTOR INC

发明人： PARK JOONBAE ,  LEE KYEONGHO ,  SONG EUNSEOK ,  JUNG YEONJAE

IPC分类号： H04B1/10 ,  H04L25/10

CPC分类号： H04B1/109

摘要： A communications receiver includes a baseband signal recovery circuit which uses a low-IF architecture for data reception. The baseband signal recovery circuit uses a full-analog implementation for channel selection and filtering. Thus, the overhead placed on the design of analog-to-digital converter is greatly relaxed and most of hardware can be re-used for multi-mode applications with only a slight modification.

公开(公告)号：EP1803216A4

公开(公告)日：2008-12-10

申请号：EP05802909

申请日：2005-09-21

申请人： GCT SEMICONDUCTOR INC

发明人： KOO YIDO ,  AHN YOUNGHO ,  SONG EUNSEOK ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC分类号： H03D3/24

CPC分类号： H03L7/0895 ,  H03L7/1976

摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PDF to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

公开(公告)号：EP1556952A4

公开(公告)日：2005-12-21

申请号：EP03779214

申请日：2003-10-23

申请人： GCT SEMICONDUCTOR INC

发明人： AHN YOUNGHO ,  SONG EUNSEOK ,  KOO YIDO ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC分类号： H03L7/197 ,  H03L7/06

CPC分类号： H03L7/1978

摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

摘要翻译： 用于改善频率发生器的信噪比的系统和方法抑制了由于内部发生器电路中的失配而产生的相位噪声和噪声。 这是利用调制方案实现的，该调制方案将发生器的环路带宽之外的寄生噪声信号移位。 当以这种方式移动时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全移除或以任何期望的程度移除。 在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。 在另一个实施例中，输入到锁相环中的参考信号被调制以实现噪声抑制。 在另一个实施例中，上述形式的调制被组合以实现期望的频移。 通过这些调制技术，频率发生器的信噪比可以显着提高，同时实现更快的锁定时间。

公开(公告)号：EP1371167A4

公开(公告)日：2005-07-13

申请号：EP02723501

申请日：2002-03-20

申请人： GCT SEMICONDUCTOR INC

发明人： HUH HYUNGKI ,  SONG EUNSEOK ,  LEE KANG YOON ,  KOO YIDO ,  LEE JEONGWOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC分类号： H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/095 ,  H03L7/197 ,  H04L7/033 ,  H04L7/00

CPC分类号： H03L7/1976 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/095

摘要： A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.