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公开(公告)号：EP1371167B1
公开(公告)日：2008-03-05
申请号：EP02723501.9
申请日：2002-03-20
发明人： HUH, Hyungki , SONG, Eunseok , LEE, Kang Yoon , KOO, Yido , LEE, Jeongwoo , PARK, Joonbae , LEE, Kyeongho
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0898 , H03L7/095
摘要： A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.
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公开(公告)号：EP1371167A1
公开(公告)日：2003-12-17
申请号：EP02723501.9
申请日：2002-03-20
发明人： HUH, Hyungki , SONG, Eunseok , LEE, Kang Yoon , KOO, Yido , LEE, Jeongwoo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04L7/00
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0898 , H03L7/095
摘要： A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.
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