公开(公告)号：EP0211336A2

公开(公告)日：1987-02-25

申请号：EP86110179.8

申请日：1986-07-24

Applicant: GTE Laboratories Incorporated

Inventor： Haselton, E. Fletcher ,  Rao, Pamidimukkala M. V. ,  Braunthal, Peter A.

IPC: H04Q11/04 ,  H04L11/20 ,  H04M11/06

CPC classification number: H04L12/64 ,  H04Q11/04

Abstract: This invention provides a port circuit (950) for coupling an end-user instrument with a port of a communications system. The communications system transmits and receives bursts via the port. A burst is a plurality of bytes which may represent, for example, a block of data or a spurt of voice energy. In a preferred embodiment, the port circuit comprises a port-interface (954), an end-user interface (958), and a microprocessor (952) coupled between the port and end-user interfaces. The microprocessor has intelligence for transmitting and receiving bursts to and from the system. The microprocessor also provides intelligence for originating and transmitting control bursts to the system and receiving and implementing control bursts from the system. A control burst is a message sent between control processors for administrative purposes. The port circuit as described is more flexible than the traditional line circuit because of the presence of the intelligent processing means. When the port circuit is adapted for coupling with an end-user voice instrument, the microprocessor includes a voice/silence detection algorithm. A port circuit may be adapted to provide one or more BORSCHT functions depending on the requirements of the particular type of end-user instrument. In various embodiments, a port circuit may include local generation of ring voltage (966), local tone detection (964), and/or a loop-back testing capability (968). A port circuit, as described herein, may be located remotely with respect to the communications system, perhaps on the user premises or even within the end-user instrument.

Abstract translation: 本发明提供了一种端口电路（950），用于耦合到终端用户设备与通信系统的端口，通信系统传送并经由端口接收的脉冲串。突发是字节的多个可以表示，例如，一个 数据的块或声音能量的突发。 在优选的实施例中的端口电路包括一个端口接口（954）到最终用户接口（958），以及耦合在所述端口和最终用户接口之间的微处理器（952）。 微处理器具有情报用于发送和接收脉冲串和从系统，该微处理器因此提供智能，以发起和发送控制脉冲串到系统，接收和处理来自系统实施控制脉冲串。一个控制脉冲串是控制处理器之间发送一个消息 administrattive目的。 如所描述的端口电路比传统线电路由于智能处理装置的存在的更灵活。 当端口电路是angepasst在最终用户的语音与仪器耦合，微处理器包括一个语音/静音检测算法。 一个端口电路可以被angepasst以提供一个或多个功能BORSCHTs取决于特定类型的最终用户仪器的要求。 在各种实施例中，一个端口电路可以包括本地代环电压（966），本地音调检测（964），和/或一个环回测试能力（968）的。 一个端口电路，如在所描述的，可以位于远程相对于该通信系统中，也许在用户场所或甚至最终用户设备内。

公开(公告)号：EP0210598A3

公开(公告)日：1989-04-05

申请号：EP86110182.2

申请日：1986-07-24

Applicant: GTE Laboratories Incorporated

Inventor： Amstutz, Stanford R. ,  Eliscu, Mark ,  Rao, Pamidimukkala M. V.

IPC: H04L11/20 ,  H04M11/06 ,  H04Q11/04 ,  H04L11/16

CPC classification number: H04Q11/04 ,  H04L12/64

Abstract: This invention provides a high-speed queue sequencer (850) which may be employed as a component of a link switch or hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the queue sequencer includes a data/address bus (862), control (860) including a stored program in a 64-bit wide PROM (852), a random-access memory (858) for queue memory which stores administrative information pertaining to bursts passing through the switch, enque means (870) for adding a burst to the list of bursts awaiting assignment to an output channel, and deque means (870) for assigning the highest-priority burst on this list to an output channel and removing the burst from the list, first-in first-out memory (868) for storing requests from switching processors and providing these requests to the control of the queue sequencer within priority class in the same time order as received, and input and output interfaces (864,866) for coupling with the switching processors. A switching processor is a companion high-speed processor employed as one or more components in a link switch and hub switch. Most components of the queue sequencer operate substantially in parallel with and independently of the control, which is a contributing factor to the speed advantage realized by the queue sequencer. The queue sequencer performs queue administration for all switching processors of a link or hub switch.

公开(公告)号：EP0211336A3

公开(公告)日：1989-03-29

申请号：EP86110179.8

申请日：1986-07-24

Applicant: GTE Laboratories Incorporated

Inventor： Haselton, E. Fletcher ,  Rao, Pamidimukkala M. V. ,  Braunthal, Peter A.

IPC: H04Q11/04 ,  H04L11/20 ,  H04M11/06

CPC classification number: H04L12/64 ,  H04Q11/04

Abstract: This invention provides a port circuit (950) for coupling an end-user instrument with a port of a communications system. The communications system transmits and receives bursts via the port. A burst is a plurality of bytes which may represent, for example, a block of data or a spurt of voice energy. In a preferred embodiment, the port circuit comprises a port-interface (954), an end-user interface (958), and a microprocessor (952) coupled between the port and end-user interfaces. The microprocessor has intelligence for transmitting and receiving bursts to and from the system. The microprocessor also provides intelligence for originating and transmitting control bursts to the system and receiving and implementing control bursts from the system. A control burst is a message sent between control processors for administrative purposes. The port circuit as described is more flexible than the traditional line circuit because of the presence of the intelligent processing means. When the port circuit is adapted for coupling with an end-user voice instrument, the microprocessor includes a voice/silence detection algorithm. A port circuit may be adapted to provide one or more BORSCHT functions depending on the requirements of the particular type of end-user instrument. In various embodiments, a port circuit may include local generation of ring voltage (966), local tone detection (964), and/or a loop-back testing capability (968). A port circuit, as described herein, may be located remotely with respect to the communications system, perhaps on the user premises or even within the end-user instrument.

Abstract translation: 本发明提供了一种用于将终端用户仪器与通信系统的端口耦合的端口电路（950）。 通信系统经由端口发送和接收脉冲串。 突发是多个字节，其可以表示例如数据块或语音能量的突发。 在优选实施例中，端口电路包括端口接口（954），终端用户接口（958）和耦合在端口与终端用户接口之间的微处理器（952）。 微处理器具有用于向系统发送和接收突发的智能。 微处理器还为系统的发起和发送控制突发提供智能，并从系统接收和实现控制脉冲串。 控制脉冲串是用于管理目的的控制处理器之间发送的消息。 由于智能处理装置的存在，所描述的端口电路比传统的线路电路更灵活。 当端口电路适于与最终用户语音仪器耦合时，微处理器包括语音/静音检测算法。 端口电路可以适于根据特定类型的最终用户仪器的要求来提供一个或多个BORSCHT功能。 在各种实施例中，端口电路可以包括本地产生环电压（966），本地音检测（964）和/或环回测试能力（968）。 如本文所述，端口电路可以相对于通信系统远程定位，可能位于用户驻地，甚至在终端用户工具内。

公开(公告)号：EP0210598A2

公开(公告)日：1987-02-04

申请号：EP86110182.2

申请日：1986-07-24

Applicant: GTE Laboratories Incorporated

Inventor： Amstutz, Stanford R. ,  Eliscu, Mark ,  Rao, Pamidimukkala M. V.

IPC: H04L11/20 ,  H04M11/06 ,  H04Q11/04 ,  H04L11/16

CPC classification number: H04Q11/04 ,  H04L12/64

Abstract: This invention provides a high-speed queue sequencer (850) which may be employed as a component of a link switch or hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the queue sequencer includes a data/address bus (862), control (860) including a stored program in a 64-bit wide PROM (852), a random-access memory (858) for queue memory which stores administrative information pertaining to bursts passing through the switch, enque means (870) for adding a burst to the list of bursts awaiting assignment to an output channel, and deque means (870) for assigning the highest-priority burst on this list to an output channel and removing the burst from the list, first-in first-out memory (868) for storing requests from switching processors and providing these requests to the control of the queue sequencer within priority class in the same time order as received, and input and output interfaces (864,866) for coupling with the switching processors. A switching processor is a companion high-speed processor employed as one or more components in a link switch and hub switch. Most components of the queue sequencer operate substantially in parallel with and independently of the control, which is a contributing factor to the speed advantage realized by the queue sequencer. The queue sequencer performs queue administration for all switching processors of a link or hub switch.