公开(公告)号：EP0829048A2

公开(公告)日：1998-03-18

申请号：EP96916908.0

申请日：1996-05-31

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： SAVKAR, Sunil ,  SHEN, Gene ,  SAJJADIAN, Farnad ,  SHEBANOW, Mike

IPC分类号： G06F9 ,  G06F11

CPC分类号： G06F11/3648

摘要： A system and method providing a programmable hardware device within a CPU. The programmable hardware device permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially.

公开(公告)号：EP0829045A1

公开(公告)日：1998-03-18

申请号：EP96919024.0

申请日：1996-05-31

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： SAVKAR, Sunil ,  SHEBANOW, Michael, C. ,  SHEN, Gene, W. ,  SAJJADIAN, Farnad

IPC分类号： G06F9

CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of the issue ordered instructions. The rotate and dispatch block including a mixer for mixing newly fetched instructions with previously fetched and unissued instructions in physical memory order, a mix and rotate device for rotating the mixed instructions into issue order, an instruction latch for holding the issue ordered instructions prior to dispatch, and an unrotate device for rotating non-issued instructions from issue order to physical memory order prior to mixing with newly fetched instructions. During the fetch cycle, multiple instructions are simultaneously fetched from storage in physical memory order and rotated into a PC-related issue order within the rotate and dispatch block. During the next clock cycle, selected ones of the previously fetched and rotated instructions enter the issue cycle, a new set of instructions are fetched in physical memory order, the previously fetched and rotated instructions which were not issued are rearranged into physical memory order and mixed in physical memory order with the newly fetched instructions, together all fetched and non-issued instructions are rotated into issue order prior to the next issue cycle, and so forth until all instructions have passed through the pipeline.