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1.发明公开METHOD AND APPARATUS FOR DETECTION OF ERRORS IN MULTIPLE-WORD COMMUNICATIONS 失效方法和系统故障检测的多个单词COMMUNICATIONS
公开(公告)号：EP0823161A1
公开(公告)日：1998-02-11
申请号：EP97906560.0
申请日：1997-02-12
CPC分类号： H04L1/0057 , H03M13/03 , H04L1/0083 , H04L69/324
摘要： A method and apparatus colors the conventional error codes of each word of a multiword transmission to facilitate the detection of bit errors in each word or words which are out of order or not part of the transmission, without affecting the data in the word. A 1-bit by n-bit matrix is assembled using the header word, and zeros for the header of the multiword transmission, or the data word, error code, if any, an identifier portion of the header word and zeros for each data word, and the 1-bit by n-bit matrix is multiplied by an n-bit by m-bit matrix assembled from a conventional error coding matrix and other matrices. The result either produces an error code to be sent with the header or data, or a check code to be verified as all zeros to indicate the absence of bit errors within the header or data word, and that the word is in the proper packet and in the proper sequence within the packet.
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2.发明公开Method and apparatus for efficiently writing results to renamed registers 失效一种用于有效地结果写入到寄存器具有改变名称的方法和装置
公开(公告)号：EP0727736A3
公开(公告)日：1997-04-16
申请号：EP96101840.5
申请日：1996-02-08
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and apparatus stores result data from an execution unit into a physical destination register in a register renaming superscaler microprocessor. The destination register number is associated with the result data and sent to a decoder which decodes the destination register number and enables the destination register corresponding to the destination register number to accept the result data broadcast to the physical destination registers.
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3.发明公开Method and apparatus for prioritizing and handling errors in a computer system 失效在计算机系统中优先和处理错误的方法和装置
公开(公告)号：EP0730230A2
公开(公告)日：1996-09-04
申请号：EP96103124.2
申请日：1996-03-01
CPC分类号： G06F11/073 , G06F11/0793
摘要： A computer system (10) includes a central processing unit (12) and a memory management unit (18) having a plurality of functional units, such as a memory interface unit, a remote interface unit (60), a cache interface unit (70), and a translation unit (50). Each functional unit has a low priority error queue for storing error information for errors having a low priority. Some functional units also have a high priority error queue for storing error information for errors having a high priority error. Based on the status of the error queues, the memory management unit prioritizes and handles errors caused by hardware failures. For low priority errors, an interrupt request signal is sent to the central processing unit (122). For high priority errors, a RED ALERT signal is sent to the processing unit (112) to cause the processing unit to give immediate attention to the error. For high priority error queue overflows, a failure signal is generated (102) which causes the system to be halted and the contents of the system to be scanned out (104). Thus, errors are prioritized and handled accordingly.
摘要翻译： 一种计算机系统（10）包括中央处理单元（12），并具有的功能单元的多个存储器管理单元（18），检查作为存储接口单元，远程接口单元（60），高速缓存接口单元（70 ），和一个翻译单元（50）。 每个功能单元具有用于存储对于具有低优先级的错误的错误信息的低优先级的错误队列。 因此，一些功能单元具有用于存储用于具有高优先级的错误的错误的错误信息高优先级错误队列。 基于错误队列的状态时，内存管理单元和优先处理由硬件故障导致的错误。 对于低优先级的错误中断请求信号被发送到中央处理单元（122）。 对于高优先级的错误，红色警报信号被发送到所述处理单元（112），以使处理单元给予立即注意到该错误。 对于高优先级的错误队列溢出时，会产生故障信号（102），从而导致系统被暂停，并且系统中的内容将被扫描出（104）。 因此，错误的优先级和相应的处理。
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公开(公告)号：EP0730226A2
公开(公告)日：1996-09-04
申请号：EP96103206.7
申请日：1996-03-01
IPC分类号： G06F9/455
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/45533
摘要： A system and method provides hardware support for fast software emulation of unimplemented instructions using issue trap logic that determines the instruction type and parameter fields of an unimplemented instruction when an exception is triggered and uses the fields to branch directly to emulation code specific to an unimplemented instruction having the determined instruction type and parameter fields.
摘要翻译： 系统和方法提供硬件支持，使用问题陷阱逻辑来快速软件仿真未实现的指令，该逻辑在异常被触发时确定未实现指令的指令类型和参数字段，并使用字段直接转移到未实现指令特有的仿真代码 具有确定的指令类型和参数字段。
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">5.发明公开Method and apparatus for storing "Don't Care" in a content addressable memory cell 失效Speicherverfahren und -anordnung zur Speicherung eines indifferenten在einer assoziative Speicherzelle的地位。
公开(公告)号：EP0660332A1
公开(公告)日：1995-06-28
申请号：EP93120844.1
申请日：1993-12-23
发明人： Montoye, Robert K.
IPC分类号： G11C15/00
摘要： A content addressable memory cell is able to store a state representing "Don't Care", by storing two bits of data. The "Don't Care" state is indicated by storing two identical bits corresponding to a predetermined value, so that the cell indicates a match regardless of the match data. When the cell is not in the "Don't Care" state, two complementary bits are stored, so that the cell indicates a match only when the match data matches the state of the first of the two bits.
摘要翻译： 内容可寻址存储单元能够通过存储两位数据来存储表示“不关心”的状态。 通过存储对应于预定值的两个相同位来指示“不关心”状态，使得小区指示匹配，而不管匹配数据如何。 当单元不处于“不关心”状态时，存储两个互补位，使得仅当匹配数据与两位中的第一位的状态匹配时，单元才指示匹配。
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6.发明公开Method and apparatus for generating a zero bit status flag in a microprocessor 失效方法和装置用于在微处理器制造Nullbitzustandsflagge
公开(公告)号：EP0730219A3
公开(公告)日：1998-07-29
申请号：EP96103210
申请日：1996-03-01
发明人： SIMONE MICHAEL A
CPC分类号： G06F9/30043 , G06F9/30094
摘要： A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to the load alignment of such data. The z-flag generator first performs a zero detect on each byte of data retrieved from memory. The zero detect results are next decoded according to bit selection signals generated from a data format code which corresponds to the specific format of the retrieved data.
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公开(公告)号：EP0834125A1
公开(公告)日：1998-04-08
申请号：EP96917217.0
申请日：1996-06-05
CPC分类号： G06F11/1008 , H03M13/15
摘要： A method and apparatus are disclosed for detecting and correcting errors in the data stored within the entries of a memory table. Each time data is entered into the memory table, an error code generator generates a corresponding error code using the data. This error code is stored in the memory table along with the corresponding data. When an entry in the memory table is read out, an error detector receives the outputted data and its corresponding error code and processes the data and the error code to determine whether the outputted data contains any errors. If the outputted data contains any errors, the outputted data and error code are sent to an error correction unit. In response, the correction unit attempts to find single and double bit errors in the data by way of a compact and efficient computer program. If either a single or double bit error is found, the error correction unit corrects the error or errors to derive a set of corrected data. This corrected data is then written back to the proper entry within the memory table to correct the error or errors in the data. Data errors within the memory table are thus detected and corrected.
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公开(公告)号：EP0829048A2
公开(公告)日：1998-03-18
申请号：EP96916908.0
申请日：1996-05-31
发明人： SAVKAR, Sunil , SHEN, Gene , SAJJADIAN, Farnad , SHEBANOW, Mike
CPC分类号： G06F11/3648
摘要： A system and method providing a programmable hardware device within a CPU. The programmable hardware device permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially.
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公开(公告)号：EP0813713A1
公开(公告)日：1997-12-29
申请号：EP96909505
申请日：1996-02-29
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1009
摘要： A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (101) (TLB) and, possibly, a translation table (116) held in memory (106) and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address (104). If exactly one valid entry of the TLB stores a translation for the specified input address then the output address (129) corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address then these entries are invalidated. A translation for the specified input address and possibly one or more translations for other input addresses that are stored together with the translation for the specified input address are taken from the translation table and inserted into the TLB.
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公开(公告)号：EP0730224A3
公开(公告)日：1997-05-28
申请号：EP96103208.3
申请日：1996-03-01
发明人： Shebanow, Michael C. , Gmuender, John , Simone, Michael A. , Szeto, John R.F.S , Maruyama, Takumi , Tovey, DeForest W.
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.
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