公开(公告)号：EP0730225A3

公开(公告)日：1999-12-08

申请号：EP96103209.1

申请日：1996-03-01

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： Shebanow, Michael C. ,  Shen, Gene W. ,  Swami, Ravi ,  Patkar, Niteen A.

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.

公开(公告)号：EP0730225A2

公开(公告)日：1996-09-04

申请号：EP96103209.1

申请日：1996-03-01

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： Shebanow, Michael C. ,  Shen, Gene W. ,  Swami, Ravi ,  Patkar, Niteen A.

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.

摘要翻译： 在微处理器中，包括用于协调微处理器中的物理寄存器的使用的装置。 在接收到指令之后，协调装置从指令中提取源和目的地逻辑寄存器。 对于目的地逻辑寄存器，设备分配一个对应于逻辑寄存器的物理地址。 这样做，该装置存储逻辑寄存器与另一物理寄存器之间的之前的关系。 存储这种以前的关系允许设备在遇到执行异常时后退到特定的指令。 此外，该装置检查指令以确定它是否是推测性分支指令。 如果是，则设备通过存储所选择的状态信息来创建检查点。 如果确定推测的分支未正确预测，则该检查点提供了处理器稍后备份的参考点。 总体而言，该装置协调处理器中物理寄存器的使用，使得：（1）逻辑/物理寄存器关系容易改变; 和（2）备份和后台程序。