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1.发明公开Method and apparatus for efficiently writing results to renamed registers 失效一种用于有效地结果写入到寄存器具有改变名称的方法和装置
公开(公告)号：EP0727736A3
公开(公告)日：1997-04-16
申请号：EP96101840.5
申请日：1996-02-08
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and apparatus stores result data from an execution unit into a physical destination register in a register renaming superscaler microprocessor. The destination register number is associated with the result data and sent to a decoder which decodes the destination register number and enables the destination register corresponding to the destination register number to accept the result data broadcast to the physical destination registers.
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2.发明公开Method and apparatus for coordinating the use of physical registers in a microprocessor 失效用于协调在一个微处理器中使用的物理寄存器的方法和设备
公开(公告)号：EP0727735A3
公开(公告)日：1997-07-02
申请号：EP96101841.3
申请日：1996-02-08
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.
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3.发明公开Method and apparatus for coordinating the use of physical registers in a microprocessor 失效用于协调在一个微处理器中使用的物理寄存器的方法和设备
公开(公告)号：EP0727735A2
公开(公告)日：1996-08-21
申请号：EP96101841.3
申请日：1996-02-08
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.
摘要翻译： 在微处理器中，以装置被包括用于协调在微处理器中使用的物理寄存器。 在接收到指令时，所述协同装置从指令中提取源和目的地的逻辑寄存器。 对于目的地逻辑寄存器，该装置分配给对应于所述逻辑寄存器的物理地址。 在这样做的装置存储的逻辑寄存器和另一个物理寄存器之间的关系前者。 存储该前关系允许当遇到异常的设备来备份步骤到一个特定的指令执行。 所以，该装置检查指令以确定性矿无论是推测性分支指令。 如果是，则该装置通过创建存储选择的状态信息的检查点。 此检查点提供了一个参考点了处理器以后可能备份，如果它是确定的开采做了推测其分支预测错误。 总体而言，该装置中的坐标求的方式在处理器中使用的物理寄存器的是：（1）逻辑/物理寄存器的关系很容易改变; 和（2）备份和回步骤程序被容纳。
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公开(公告)号：EP0730224A3
公开(公告)日：1997-05-28
申请号：EP96103208.3
申请日：1996-03-01
发明人： Shebanow, Michael C. , Gmuender, John , Simone, Michael A. , Szeto, John R.F.S , Maruyama, Takumi , Tovey, DeForest W.
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.
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公开(公告)号：EP0730224A2
公开(公告)日：1996-09-04
申请号：EP96103208.3
申请日：1996-03-01
发明人： Shebanow, Michael C. , Gmuender, John , Simone, Michael A. , Szeto, John R.F.S , Maruyama, Takumi , Tovey, DeForest W.
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution.
An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.摘要翻译： 指令选择器每个时钟周期接收M个指令，并将N个指令存储在指令队列存储器中。 指令队列产生指示N个指令的年龄的优先矩阵。 依赖检查器确定用于执行准备执行的指令的可用寄存器。 最古老的指令选择器根据优先矩阵和符合条件的队列输入信号来选择M个最旧的指令。 指令队列将M个选择的指令提供给执行单元以供执行。 完成指令后，执行单元向依赖检查器提供寄存器可用性信号，以释放用于指令的寄存器。
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6.发明公开Method and apparatus for efficiently writing results to renamed registers 失效一种用于有效地结果写入到寄存器具有改变名称的方法和装置
公开(公告)号：EP0727736A2
公开(公告)日：1996-08-21
申请号：EP96101840.5
申请日：1996-02-08
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and apparatus stores result data from an execution unit into a physical destination register in a register renaming superscaler microprocessor. The destination register number is associated with the result data and sent to a decoder which decodes the destination register number and enables the destination register corresponding to the destination register number to accept the result data broadcast to the physical destination registers.
摘要翻译： 的方法和装置存储产生于在执行单元数据转换成在寄存器重命名的超标量微处理器的物理目的地寄存器。 目的地寄存器编号与结果数据相关联，并且发送到解码器，其解码目的地寄存器编号，并且使目的寄存器对应于目的地寄存器编号接受广播到物理目的地寄存器中的结果的数据。
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