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6 条记录 (耗时 0.008 秒)

    Programmable controller and sequence control method
    1.
    发明公开
    Programmable controller and sequence control method 失效
    程序员Steuergerätund Verfahren zur sequentiellen Steuerung。

    公开(公告)号：EP0539115A2

    公开(公告)日：1993-04-28

    申请号：EP92309459.3

    申请日：1992-10-16

    申请人： HITACHI, LTD.

    发明人： Kobayashi, Mitsuaki ,  Matsuda, Toshihiko ,  Morooka, Yasuo ,  Onuma, Kunihiko ,  Azusawa, Noboru ,  Kikuchi, Hiromitsu

    IPC分类号： G06F9/30 ,  G05B19/05

    CPC分类号： G06F9/30145 ,  G05B19/052 ,  G06F9/30018 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3885

    摘要： The present specification discloses a programmable controller which comprises bit operation memory for storing a mixed instruction inclusive of the mixture of bit operation instructions and word operation instructions in order of execution; a word operation memory for storing the word operation instructions in said mixed instruction in order of execution; a bit operation processor for outputting a start command for a word operation instruction when recognizing that word operation instruction read from said bit operation memory subsequently to the execution of the bit operation instruction; and a microprocessor for receiving said word operation start command to execute said word operation instruction stored in said word operation memory.

    摘要翻译： 本说明书公开了一种可编程控制器，其包括位操作存储器，用于按照执行顺序存储包含位操作指令和字操作指令的混合的混合指令; 字操作存储器，用于按照执行顺序将所述字操作指令存储在所述混合指令中; 一位操作处理器，用于在识别从所述位操作存储器读取的字操作指令之后执行位操作指令时，输出用于字操作指令的开始命令; 以及微处理器，用于接收所述字操作开始命令以执行存储在所述字操作存储器中的所述字操作指令。

    Programmable controller and sequence control method
    5.
    发明公开
    Programmable controller and sequence control method 失效
    可编程控制器和序列控制方法

    公开(公告)号：EP0539115A3

    公开(公告)日：1994-11-09

    申请号：EP92309459.3

    申请日：1992-10-16

    申请人： HITACHI, LTD.

    发明人： Kobayashi, Mitsuaki ,  Matsuda, Toshihiko ,  Morooka, Yasuo ,  Onuma, Kunihiko ,  Azusawa, Noboru ,  Kikuchi, Hiromitsu

    IPC分类号： G06F9/30 ,  G05B19/05

    CPC分类号： G06F9/30145 ,  G05B19/052 ,  G06F9/30018 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3885

    摘要： The present specification discloses a programmable controller which comprises bit operation memory for storing a mixed instruction inclusive of the mixture of bit operation instructions and word operation instructions in order of execution; a word operation memory for storing the word operation instructions in said mixed instruction in order of execution; a bit operation processor for outputting a start command for a word operation instruction when recognizing that word operation instruction read from said bit operation memory subsequently to the execution of the bit operation instruction; and a microprocessor for receiving said word operation start command to execute said word operation instruction stored in said word operation memory.

    摘要翻译： 本说明书公开了一种可编程控制器，其包括位操作存储器，用于按照执行顺序存储包含位操作指令和字操作指令的混合的混合指令; 字操作存储器，用于按照执行顺序将所述字操作指令存储在所述混合指令中; 一位操作处理器，用于在识别从所述位操作存储器读取的字操作指令之后执行位操作指令时，输出用于字操作指令的开始命令; 以及微处理器，用于接收所述字操作开始命令以执行存储在所述字操作存储器中的所述字操作指令。

    Data transmission bus system for a plurality of processors
    6.
    发明公开
    Data transmission bus system for a plurality of processors 失效
    Datenübertragungsbussystemfürmehrere Prozessoren。

    公开(公告)号：EP0076494A2

    公开(公告)日：1983-04-13

    申请号：EP82109102.2

    申请日：1982-10-01

    申请人： Hitachi, Ltd.

    发明人： Takakura, Mitsuro ,  Shimoyama, Kazuhiko ,  Okamoto, Tadashi ,  Azusawa, Noboru ,  Yoshida, Takenari ,  Saito, Yutaka ,  Sakurai, Takakazu ,  Kitani, Susumu ,  Kikuchi, Yuji ,  Kamigane, Yoshihiro

    IPC分类号： G06F13/00 ,  G06F15/16

    CPC分类号： G06F15/161 ,  G06F13/366

    摘要： A data transmission system for transferring data between a plurality of processors (200A - 200G, 200Z, 2000) and between the processors and an input/output unit (303) through a common bus (301) has linkage units (300A - 300G, 300Z, 300L) between the processors and the bus and an address controller (302) to manage the bus. Each of the linkage units has a two-port random access memory (42A - 42G) for storing data necessary for the processor. The processor processes the data stored in the memory and writes a result of the processing in an output area of the memory. The processing of the processors and the data transfer through the bus are essentially separated and carried out independently.

    摘要翻译： 用于通过公共总线（301）在多个处理器（200A-200G，200Z，2000）之间以及处理器与输入/输出单元（303）之间传送数据的数据传输系统具有连接单元（300A-300G，300Z ，300L）和地址控制器（302）之间，用于管理总线。 每个联动单元具有用于存储处理器所需的数据的双端口随机存取存储器（42A-42G）。 处理器处理存储在存储器中的数据，并将处理结果写入存储器的输出区域。 处理器的处理和通过总线的数据传输基本上是分开的，并且是独立执行的。