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1.发明公开Virtual long instruction word memory architecture for digital signal processor 失效Virtuelle Langebefehlswortspeicherarchitekturfürdigitalen Signalprozessor。
公开(公告)号：EP0473420A2
公开(公告)日：1992-03-04
申请号：EP91307890.3
申请日：1991-08-28
申请人： HITACHI, LTD.
发明人： Haigh, Stephen G. , Baji, Toru
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3885
摘要： An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate along instruction word when the predefined criteria are not met. In that case, the second instruction may be accessed again during the next instruction fetch cycle as the first of two adjacent instructions.
摘要翻译： 用于数据处理单元的指令存储装置存储指令序列。 在每个指令获取周期，访问两个顺序相邻的指令。 当两个指令满足预定义的组合标准时，耦合到内部指令存储器的指令预处理单元将两个顺序相邻的指令组合成单个长指令字。 当不符合预定义的标准时，两个指令中的第一个与无操作指令组合以产生指令字。 在这种情况下，可以在下一指令获取周期期间再次访问第二指令作为两个相邻指令中的第一指令。
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2.发明公开Virtual long instruction word memory architecture for digital signal processor 失效数字信号处理器的虚拟长度指令记忆体架构
公开(公告)号：EP0473420A3
公开(公告)日：1993-10-13
申请号：EP91307890.3
申请日：1991-08-28
申请人： HITACHI, LTD.
发明人： Haigh, Stephen G. , Baji, Toru
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3885
摘要： An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate along instruction word when the predefined criteria are not met. In that case, the second instruction may be accessed again during the next instruction fetch cycle as the first of two adjacent instructions.
摘要翻译： 用于数据处理单元的指令存储装置存储指令序列。 在每个指令获取周期，访问两个顺序相邻的指令。 当两个指令满足预定义的组合标准时，耦合到内部指令存储器的指令预处理单元将两个顺序相邻的指令组合成单个长指令字。 当不符合预定义的标准时，两个指令中的第一个与无操作指令组合以产生指令字。 在这种情况下，可以在下一指令获取周期期间再次访问第二指令作为两个相邻指令中的第一指令。
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