公开(公告)号：EP0169540A3

公开(公告)日：1987-02-04

申请号：EP85109200

申请日：1985-07-23

申请人： HITACHI, LTD.

发明人： Kobayashi, Masaharu 331, Hitachi-Hachimanyama ,  Okamoto, Hiroo ,  Arai, Takao

IPC分类号： G11B20/18

CPC分类号： G11B20/1809

摘要： In a stationary head type PCM recorder having an AID converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay means (4-8) for adding an error detection and correction code and a predetermined signal to the digital signal for each error correction group of a predetermined number of samples, and a multi-track head for recording an output of the signal processing circuit on a plurality of tracks of a magnetic record medium and reproducing the signals recorded on the magnetic record medium; incorrectability of the error detection and correction code for a burst error in the output analog signal due to a burst error in the reproduced output is reduced by delaying parity words by the error detection and correction code and the digital signal data by different delay times such that the digital signal data are dispersely recorded in a track direction and a tape transport direction, and allotting the delayed data to the multi-track head such that the data of the adjacent sample points are spaced from each other by at least the distribution length of the parity words and the parity words is arranged between the distributed adjacent data.