公开(公告)号：EP0637800B1

公开(公告)日：2003-02-19

申请号：EP94305771.1

申请日：1994-08-03

申请人： Hitachi, Ltd.

发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

公开(公告)号：EP1256879A2

公开(公告)日：2002-11-13

申请号：EP02014525.6

申请日：1994-08-03

申请人： Hitachi, Ltd.

发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

摘要翻译： 数据处理器具有存储由处理器使用的数据和指令的主存储器（203），指令处理器（201）和两个高速缓存存储器（100,101）。 第一高速缓冲存储器（101）是大容量端口直接映射高速缓存存储器，第二高速缓存存储器（100）是小容量二端口组关联高速缓冲存储器。 指令处理器（201）根据来自主存储器的指令来控制向高速缓冲存储器（100,102）传输数据，从而频繁地存储所需的数据存储在第一高速缓冲存储器（101）中，并且数据需要较少 存储在第二高速缓冲存储器（100）中。 通过这样的布置，存储在第二高速缓冲存储器（100）中的数据可以在其被访问之后被移除，并且存储在其中的其他数据，从而增加在任何时间所需的数据将在第一或第二高速缓冲存储器 （101,100），而不在第一高速缓存存储器（101）上存储无用的数据。

公开(公告)号：EP1256879A3

公开(公告)日：2005-02-09

申请号：EP02014525.6

申请日：1994-08-03

申请人： Hitachi, Ltd.

发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

公开(公告)号：EP1901170A1

公开(公告)日：2008-03-19

申请号：EP07016550.1

申请日：1994-08-03

申请人： Hitachi, Ltd.

发明人： Hotta, Takahashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

摘要翻译： 数据处理器具有存储由处理器使用的数据和指令的主存储器（203），指令处理器（201）和两个高速缓存存储器（100,101）。 第一高速缓冲存储器（101）是大容量端口直接映射高速缓存存储器，第二高速缓存存储器（100）是小容量二端口组关联高速缓冲存储器。 指令处理器（201）根据来自主存储器的指令来控制向高速缓冲存储器（100,102）传输数据，从而频繁地存储所需的数据存储在第一高速缓冲存储器（101）中，并且数据需要较少 存储在第二高速缓冲存储器（100）中。 通过这样的布置，存储在第二高速缓冲存储器（100）中的数据可以在其被访问之后被移除，并且存储在其中的其他数据，从而增加在任何时间所需的数据将在第一或第二高速缓冲存储器 （101,100），而不在第一高速缓存存储器（101）上存储无用的数据。

公开(公告)号：EP0637800A3

公开(公告)日：1995-07-19

申请号：EP94305771.1

申请日：1994-08-03

申请人： HITACHI, LTD.

发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

公开(公告)号：EP0637800A2

公开(公告)日：1995-02-08

申请号：EP94305771.1

申请日：1994-08-03

申请人： HITACHI, LTD.

发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

摘要翻译： 数据处理器具有存储由处理器，指令处理器（201）和两个高速缓冲存储器（100,101）使用的数据和指令的主存储器（203）。 第一高速缓冲存储器（101）是大容量端口直接映射高速缓冲存储器，第二高速缓冲存储器（100）是小容量双端口组相联高速缓冲存储器。 指令处理器（201）根据来自主存储器的指令控制与高速缓冲存储器（100,102）之间的数据传送，使得频繁需要的数据被存储在第一高速缓冲存储器（101）中，并且所需数据较少 被存储在第二高速缓冲存储器（100）中。 利用这样的安排，存储在第二高速缓冲存储器（100）中的数据可以在其被访问之后从其中删除，并且其中存储的其他数据由此增加了随时需要的数据将会在第一或第二高速缓冲存储器 （101,100），而不在第一高速缓冲存储器（101）上存储无用数据。