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29 条记录 (耗时 0.014 秒)

    Memory access methods in a unified memory system
    1.
    发明公开
    Memory access methods in a unified memory system 审中-公开
    在一个统一的存储系统存储器访问方法

    公开(公告)号：EP1182640A3

    公开(公告)日：2007-09-26

    申请号：EP01104157.1

    申请日：2001-02-21

    申请人： Hitachi, Ltd.

    发明人： Nakatsuka, Yasuhiro ,  Shimomura, Tetsuya ,  Jyou, Manabu ,  Morita, Yuichiro ,  Hotta, Takashi ,  Yamagishi, Kazushige ,  Okada, Yukata

    IPC分类号： G09G5/36

    CPC分类号： G09G5/39 ,  G09G2360/125

    摘要： The basic section of the multimedia data-processing system comprises CPU 1100, image display unit 2100, unified memory 1200, system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

    Data processor having cache memory
    2.
    发明公开
    Data processor having cache memory 失效
    数据处理器缓存

    公开(公告)号：EP1256879A3

    公开(公告)日：2005-02-09

    申请号：EP02014525.6

    申请日：1994-08-03

    申请人： Hitachi, Ltd.

    发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

    摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

    Image processor, image processing apparatus and image processing method
    3.
    发明公开
    Image processor, image processing apparatus and image processing method 失效
    图像处理器，设备，和图像处理的方法

    公开(公告)号：EP0851383A3

    公开(公告)日：2000-01-05

    申请号：EP97122659.2

    申请日：1997-12-22

    申请人： Hitachi, Ltd.

    发明人： Ikeda, Mitsuji ,  Yoshida, Syoji ,  Nakashima, Keisuke ,  Katsura, Koyo ,  Shibukawa, Shigeru ,  Yoda, Haruo ,  Hotta, Takashi

    IPC分类号： G06K9/64 ,  G06T5/20

    CPC分类号： G06K9/6203 ,  G06T7/20

    摘要： An image processing apparatus obtains a sum A of image data values of pixels in a template image, a sum B of squares of image data values of pixels in a template image, a sum C of image data values of pixels in a sub-image to be processed, of a search image, a sum D of squares of image data values of pixels in the sub-image of the template image, further obtains a threshold value F in advance by using the obtained values A, B, C and D, the number P of pixels in the template image, and the preset value E. Moreover, the apparatus obtains a square of each difference between an image data value of each pixel in the sub-image and that of a corresponding pixel in the template image, and performs cumulative addition for each obtained squares. If the result of cumulative addition exceeds the above-mentioned threshold value, the apparatus closes processing evaluation of a similarity between the sub-image and the template image. Furthermore, the apparatus recursively obtains a moving-average value of image data values of pixels in a rectangular region to be presently processed, by using a moving-average value for a rectangular region which was previously processed and image data read from a first memory and a second memory, each memory stores image data by one line pixels of the image, which include image data of pertinent pixels in the rectangular regions.

    Data processor
    7.
    发明公开
    Data processor 失效
    空值

    公开(公告)号：EP0782071A3

    公开(公告)日：1997-07-30

    申请号：EP97103969.8

    申请日：1989-11-10

    申请人： HITACHI, LTD.

    发明人： Hotta, Takashi ,  Tanaka, Shigeya ,  Maejima, Hideo

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3889 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3885

    摘要： The data processor for executing in a pipeline system instructions controlled by wired logic control includes a plurality of instruction registers (104, 105; 3204 -3207) and arithmetic operation units (110, 112; 3214, 3215, 3217, 3218) of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

    摘要翻译： 用于在管线系统中执行的用于由有线逻辑控制控制的指令的数据处理器包括多个指令寄存器（104,105; 3204-3207）和相同的数学运算单元（110,112; 3214,3215,3217,3218） 数。 一次在一个机器周期中在指令寄存器中读取的多个指令由多个算术运算单元并行处理。

    Data processor
    8.
    发明公开
    Data processor 失效
    数据处理器

    公开(公告)号：EP0782071A2

    公开(公告)日：1997-07-02

    申请号：EP97103969.8

    申请日：1989-11-10

    申请人： HITACHI, LTD.

    发明人： Hotta, Takashi ,  Tanaka, Shigeya ,  Maejima, Hideo

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3889 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3885

    摘要： The data processor for executing in a pipeline system instructions controlled by wired logic control includes a plurality of instruction registers (104, 105; 3204 -3207) and arithmetic operation units (110, 112; 3214, 3215, 3217, 3218) of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

    摘要翻译： 用于在流水线系统中执行的由有线逻辑控制控制的指令的数据处理器包括相同的多个指令寄存器（104,105; 3204-3207）和算术运算单元（110,112; 3214,3215,3217,3218） 数。 由多个算术运算单元并行处理在一个机器周期中在指令寄存器中读取的多个指令。

    Data processor having cache memory
    9.
    发明公开
    Data processor having cache memory 失效
    数据处理器缓存。

    公开(公告)号：EP0637800A3

    公开(公告)日：1995-07-19

    申请号：EP94305771.1

    申请日：1994-08-03

    申请人： HITACHI, LTD.

    发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

    摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

    Data processor having cache memory
    10.
    发明公开
    Data processor having cache memory 失效
    数据处理器具有高速缓存

    公开(公告)号：EP0637800A2

    公开(公告)日：1995-02-08

    申请号：EP94305771.1

    申请日：1994-08-03

    申请人： HITACHI, LTD.

    发明人： Hotta, Takashi ,  Kurihara, Toshihiko ,  Tanaka, Shigeya ,  Sawamoto, Hideo ,  Osumi, Akiyoshi ,  Saito, Koji ,  Shimamura, Kotaro

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

    摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

    摘要翻译： 数据处理器具有存储由处理器，指令处理器（201）和两个高速缓冲存储器（100,101）使用的数据和指令的主存储器（203）。 第一高速缓冲存储器（101）是大容量端口直接映射高速缓冲存储器，第二高速缓冲存储器（100）是小容量双端口组相联高速缓冲存储器。 指令处理器（201）根据来自主存储器的指令控制与高速缓冲存储器（100,102）之间的数据传送，使得频繁需要的数据被存储在第一高速缓冲存储器（101）中，并且所需数据较少 被存储在第二高速缓冲存储器（100）中。 利用这样的安排，存储在第二高速缓冲存储器（100）中的数据可以在其被访问之后从其中删除，并且其中存储的其他数据由此增加了随时需要的数据将会在第一或第二高速缓冲存储器 （101,100），而不在第一高速缓冲存储器（101）上存储无用数据。