公开(公告)号：EP1096684A3

公开(公告)日：2001-09-12

申请号：EP01100167.4

申请日：1996-07-25

申请人： Hitachi, Ltd.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi 221 Hitachi-Hachimanyama-Apt1545 ,  Urata, Hiroyuki ,  Iwanaga, Masaaki

IPC分类号： H03L7/085 ,  H03M1/12

CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20

摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.

摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO由AID转换器4与写入控制电路5中产生的采样时钟同步地转换为8位数据， 然后存储在存储器6中。MPU9读出存储在存储器6中的视频信号的有效区域中的像素数据，并计算其值较大的白电平像素数据的平均值之间的差ΔT 超过预定值，并且其值小于预定值的黑电平图像元素数据的平均值，以及白电平图像元素数据的方差与黑电平像素的方差之间的总方差VT 数据。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大并且VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。

公开(公告)号：EP0756417B1

公开(公告)日：2001-10-17

申请号：EP96112008.6

申请日：1996-07-25

申请人： Hitachi, Ltd.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi, 221, Hitachi-Hachimanyama-Apt. ,  Urata, Hiroyuki ,  Iwanaga, Masaaki

IPC分类号： H04N5/12 ,  H03L7/085

CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20

公开(公告)号：EP0803855A3

公开(公告)日：1999-06-16

申请号：EP97106459.7

申请日：1997-04-18

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi ,  Urata, Hiroyuki ,  Takata, Haruki

IPC分类号： G09G3/20

CPC分类号： G06T3/4007 ,  G09G5/005 ,  G09G5/006 ,  G09G5/008 ,  G09G2300/026 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442

摘要： A video signal processor which includes a circuit (108) for converting the number of lines in a digitized video signal, a circuit (109) for generating a display dot clock, a circuit (110) for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit (111) for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation; frck/N = fck/M = fho where M and N are natural numbers satisfying M ≠ N .

公开(公告)号：EP1096684B1

公开(公告)日：2004-01-28

申请号：EP01100167.4

申请日：1996-07-25

申请人： Hitachi, Ltd.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi 221 Hitachi-Hachimanyama-Apt1545 ,  Urata, Hiroyuki ,  Iwanaga, Masaaki

IPC分类号： H04N5/04 ,  H03L7/085 ,  H03M1/12

CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20

公开(公告)号：EP0756417A2

公开(公告)日：1997-01-29

申请号：EP96112008.6

申请日：1996-07-25

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi, 221, Hitachi-Hachimanyama-Apt. ,  Urata, Hiroyuki ,  Iwanaga, Masaaki

IPC分类号： H04N5/12

CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20

摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.

摘要翻译： 在视频信号处理装置中，表示具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 MPU 9存储在存储器6中的视频信号的有效区域中读出图像元素数据，并计算出在其值为0的白电平图像元素数据的平均值之间的差ΔT 大于预定值，并且其值小于预定值的黑电平图像元素数据的平均值以及白电平图像元素数据的方差与黑电平的方差之间的总方差VT 图片元素数据。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大并且VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。

公开(公告)号：EP1096684A2

公开(公告)日：2001-05-02

申请号：EP01100167.4

申请日：1996-07-25

申请人： Hitachi, Ltd.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi 221 Hitachi-Hachimanyama-Apt1545 ,  Urata, Hiroyuki ,  Iwanaga, Masaaki

IPC分类号： H03L7/085

CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20

摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.

摘要翻译： 在视频信号处理装置中，代表具有两个黑色和白色等级的测试图案的输入视频信号VO由AID转换器4与写入控制电路5中产生的采样时钟同步地转换为8位数据， 然后存储在存储器6中.MPU9读出存储在存储器6中的视频信号的有效区域中的图像元素数据，并且计算其值较大的白色级图像元素数据的平均值 比预定值和其值小于预定值的黑电平图像元素数据的平均值以及白电平图像元素数据的方差与黑电平图像元素的方差之间的总变化VT 数据。 MPU9控制写入控制电路5中产生的采样时钟的相位，使得AT最大并且VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可自动调整到最佳值。

公开(公告)号：EP0803855A2

公开(公告)日：1997-10-29

申请号：EP97106459.7

申请日：1997-04-18

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi ,  Urata, Hiroyuki ,  Takata, Haruki

IPC分类号： G09G3/20

CPC分类号： G06T3/4007 ,  G09G5/005 ,  G09G5/006 ,  G09G5/008 ,  G09G2300/026 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442

摘要： A video signal processor which includes a circuit (108) for converting the number of lines in a digitized video signal, a circuit (109) for generating a display dot clock, a circuit (110) for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit (111) for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation; frck/N = fck/M = fho where M and N are natural numbers satisfying M ≠ N .

摘要翻译： 一种视频信号处理器，其包括用于，电路（109）转换的行数在一个数字化的视频信号，用于进行行号输出婷模拟像素数据生成显示点时钟的电路（110）的电路（108） 转换并具有从所述显示不同的频率做点时钟，以及用于平滑模拟像素数据的电路（111）; 和其中显示点时钟将模拟像素数据和水平同步信号SATIS外资企业等式的频率FHO的输出频率FRK的频率FCK; $其中M和N是满足M注QUAL\; N.e自然数$

公开(公告)号：EP0756417A3

公开(公告)日：1997-06-11

申请号：EP96112008.6

申请日：1996-07-25

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi, 221, Hitachi-Hachimanyama-Apt. ,  Urata, Hiroyuki ,  Iwanaga, Masaaki

IPC分类号： H04N5/12

CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20

摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.