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21 条记录 (耗时 0.015 秒)

    Cursor display control method and apparatus in a graphic display system
    2.
    发明公开
    Cursor display control method and apparatus in a graphic display system 失效
    Verfahren und Vorrichtung zur Steuerung der Kursordarstellung in graphischen Anzeigesystemen。

    公开(公告)号：EP0418859A1

    公开(公告)日：1991-03-27

    申请号：EP90118022.4

    申请日：1990-09-19

    申请人： HITACHI, LTD. ,  Hitachi Engineering Co., Ltd.

    发明人： Matsuo, Shigeru ,  Fukushima, Tadashi ,  Komagawa, Tooru ,  Narita, Masahisa

    IPC分类号： G09G5/08

    CPC分类号： G09G5/08

    摘要： A cursor display control in a graphic display system is provided in which a storage range is provided for exclusive use for a cursor pattern and a desired shape is defined in the storage range to thereby perform a high-speed cursor movement. A display control apparatus in the graphic display system includes a memory (510, 520) for storing a cursor pattern, shift register (530) for performing a shift processing in a non-display period of the cursor for positioning in the display screen, and parallel-serial converter (101, 103) for performing parallel to serial conversion at the display timing of the cursor, whereby the apparatus is suitable to be integrated in the form of an LSI and the cursor can be moved at a high speed on the screen.

    摘要翻译： 提供了图形显示系统中的光标显示控制，其中存储范围被提供用于光标图案的专用，并且在存储范围内定义期望的形状，从而执行高速光标移动。 图形显示系统中的显示控制装置包括用于存储光标图形的存储器（510,520），用于在用于定位在显示屏幕中的光标的非显示时段执行移位处理的移位寄存器（530），以及 并行串行转换器（101,103），用于在光标的显示定时执行并行转换，从而该装置适于以LSI的形式集成，并且可以在屏幕上高速移动光标 。

    Parallel image processor
    3.
    发明公开
    Parallel image processor 失效
    平行Bildverarbeitungsgerät。

    公开(公告)号：EP0189943A2

    公开(公告)日：1986-08-06

    申请号：EP86101338.1

    申请日：1986-01-31

    申请人： HITACHI, LTD.

    发明人： Miura, Shuuichi ,  Kobayashi, Yoshiki ,  Fukushima, Tadashi ,  Okuyama, Yoshiyuki ,  Katoh, Takeshi ,  Hirasawa, Kotaro ,  Asada, Kazuyoshi

    IPC分类号： G06F15/68

    CPC分类号： G06T5/20

    摘要： An LSI parallel image processor in which line buffers (20-i) and data-flow switching circuits (70) each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers (20-i) is output from an image data output port (55), shift registers (31-i) each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers (31-i) are sequentially read out.

    摘要翻译： LSI现有技术中需要较大硬件量的行缓冲器（20-i）和数据流切换电路（70）的LSI并行图像处理器被并入到LSI电路中，由行缓冲器 20-i）从图像数据输出端口（55）输出，每个具有可变数目的用于保存局部图像区域的移位寄存器（31-i）根据施加的时钟间歇地移入，并且内容 顺序地读出移位寄存器（31-i）。

    Multifunctional image processor
    4.
    发明公开
    Multifunctional image processor 失效
    多功能图像处理器

    公开(公告)号：EP0150060A3

    公开(公告)日：1986-07-30

    申请号：EP85100507

    申请日：1985-01-18

    申请人： HITACHI, LTD.

    发明人： Kobayashi, Yoshiki ,  Fukushima, Tadashi ,  Okuyama, Yoshiyuki ,  Hirasawa, Kotaro ,  Kato, Takeshi ,  Kubo, Yutaka

    IPC分类号： G06F15/66

    CPC分类号： G06T1/20

    摘要： A multifunctional image processor capable of executing a variety of image processing functions such as a spatial convolution and a color image processing at a higher speed includes an image data distribute unit (31) for distributing the gray-scale and color image data externally supplied by use of programs in accordance with the operation of the image processing and a parallel image data processing unit (32) for .conducting a parallel operation on distributed image data in accordance with the operation of the image processing.

    Micoprocessor, and graphics processing apparatus and method using the same
    6.
    发明公开
    Micoprocessor, and graphics processing apparatus and method using the same 失效
    米克罗教授，Bildverarbeitungsgerätund Verfahren，das diesebenützt

    公开(公告)号：EP0807900A1

    公开(公告)日：1997-11-19

    申请号：EP97112431.8

    申请日：1990-04-20

    申请人： HITACHI, LTD.

    发明人： Yamada, Hiromichi ,  Fukushima, Tadashi ,  Matsuo, Shigeru ,  Miyamoto, Takashi ,  Komagawa, Toru ,  Yoshida, Shoji

    IPC分类号： G06T1/20

    CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3879 ,  G06F15/7832 ,  G06T1/20

    摘要： A microprocessor comprises a processor unit (101) for decoding and executing an instruction, two ports (102, 103) each for transferring address, data and control signals between each of said ports and a respective memory connected thereto, and address buffer (1201-1, 1301-1) writable from said processor unit (101) and readable from said two ports (102, 103), a data buffer (1201-, 1301-2; 1201-3, 1301-3) which is readable and writable from said two ports (102, 103) and from which an instruction may be read by said processor unit (101), and means for controlling an address transfer from said address buffer to one of the memories and also a data transfer between said data buffer and one of the memories via the designated port according to a memory access request and a port designating signal from said processor unit, whereby an instruction fetch and a data access can be performed with respect to the two memories,

    摘要翻译： 微处理器包括用于解码和执行指令的处理器单元（101），两个端口（102,103），每个用于在每个所述端口和连接到其之间的相应存储器之间传送地址，数据和控制信号;以及地址缓冲器 1，1301-1），可从所述处理器单元（101）写入并且可从所述两个端口（102,103）读取，数据缓冲器（1201,1301,1201-3,1301-3），其是可读写的 来自所述两个端口（102,103），并且所述处理器单元（101）可以从其读取指令;以及用于控制从所述地址缓冲器到所述存储器之一的地址传送的装置，以及所述数据缓冲器 和根据存储器访问请求的指定端口的一个存储器和来自所述处理器单元的端口指定信号，从而可以针对两个存储器执行指令获取和数据访问，

    Image signal processor
    8.
    发明公开
    Image signal processor 失效
    图像信号处理器

    公开(公告)号：EP0118053A3

    公开(公告)日：1986-08-13

    申请号：EP84101305

    申请日：1984-02-08

    申请人： HITACHI, LTD.

    发明人： Fukushima, Tadashi ,  Kobayashi, Yoshiki ,  Okuyama, Yoshiyuki ,  Katoh, Takeshi ,  Kashioka, Seiji

    IPC分类号： G06F15/20 ,  G06F15/68 ,  G06F15/66

    CPC分类号： G06T1/20

    摘要： A high speed, multi-function and expandable image processing LSI (image signal processor) for realizing density image processing technique has been developed. An architecture of the image signal processor (ISP) which can process a density image having 256 tones at a video rate (256 x 256 image, 6MHz, non-interlace), allows expansion of a partial operation area (kernel) and can carry out various partial neighbourhood operation, is disclosed. The image signal processor (ISP) is a partial parallel type image processing LSI which carries out a parallel operation by using the same number of processor elements (PE's) as that of input pixel data used to produce one output pixel data.

    Parallel image processor
    10.
    发明公开
    Parallel image processor 失效
    并行图像处理器

    公开(公告)号：EP0189943A3

    公开(公告)日：1988-12-14

    申请号：EP86101338

    申请日：1986-01-31

    申请人： HITACHI, LTD.

    发明人： Miura, Shuuichi ,  Kobayashi, Yoshiki ,  Fukushima, Tadashi ,  Okuyama, Yoshiyuki ,  Katoh, Takeshi ,  Hirasawa, Kotaro ,  Asada, Kazuyoshi

    IPC分类号： G06F15/68

    CPC分类号： G06T5/20

    摘要： An LSI parallel image processor in which line buffers (20-i) and data-flow switching circuits (70) each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers (20-i) is output from an image data output port (55), shift registers (31-i) each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers (31-i) are sequentially read out.