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15 条记录 (耗时 0.016 秒)

    Thermal mass flow sensor
    1.
    发明公开
    Thermal mass flow sensor 审中-公开
    Thermischer Massendurchflusssensor

    公开(公告)号：EP1657532A1

    公开(公告)日：2006-05-17

    申请号：EP05018073.6

    申请日：2005-08-19

    申请人： HITACHI, LTD.

    发明人： Hanzawa, Keiji ,  Matsumoto, Masahiro ,  Yamada, Hiromichi ,  Nakano, Hiroshi ,  Sukesako, Hiroyasu

    IPC分类号： G01F1/698

    CPC分类号： G01F1/6845 ,  G01F1/696 ,  G01F1/6986 ,  G01F1/699

    摘要： The present invention relates to an air flowmeter in which an air flow rate sensing element and air temperature sensing element are integrated with each other and mounted on a substrate and at the same time the fluid temperature sensing element is formed on a diaphragm, the fluid flowmeter being capable of measuring a fluid flow rate with high accuracy by suppressing the self-heating of the fluid temperature sensing element.
    In the invention, an air temperature sensor 11 sensing an air temperature, supplied with a pulse signal as a driving signal from a pulse signal source 19, senses an air temperature based on the pulse signal. While the air temperature sensor 11 is self-heated during an electrical current supplying time period by the pulse signal, it is cooled during an electrical current halting time period. Accordingly, the self-heating of the air temperature sensor 11 by the driving signal is suppressed, and a thermal effect on air flow rate sensing elements 5 to 10 disposed in an air flow downstream side of the air temperature sensor 11 is also reduced.

    摘要翻译： 本发明涉及一种空气流量计，其中空气流量感测元件和空气温度感测元件彼此集成并安装在基板上，同时流体温度感测元件形成在隔膜上，流体流量计 能够通过抑制流体温度感测元件的自身加热而能够高精度地测量流体流量。 在本发明中，感测从脉冲信号源19提供作为驱动信号的脉冲信号的空气温度的空气温度传感器11基于脉冲信号感测空气温度。 空气温度传感器11在通过脉冲信号的电流供给时间段内自加热时，在电流停止时间段内被冷却。 因此，通过驱动信号来抑制空气温度传感器11的自身加热，并且对于设置在空气温度传感器11的空气流下游侧的空气流量检测元件5〜10的热效应也降低。

    Microprocessor, and graphics processing apparatus and method using the same
    3.
    发明公开
    Microprocessor, and graphics processing apparatus and method using the same 失效
    微处理器以及使用其的图形处理设备和方法

    公开(公告)号：EP1158462A1

    公开(公告)日：2001-11-28

    申请号：EP01106437.5

    申请日：1990-04-20

    申请人： Hitachi Ltd.

    发明人： Yamada, Hiromichi ,  Fukushima, Tadashi ,  Matsuo, Shigeru ,  Miyamoto, Takashi ,  Komagawa, Toru ,  Yoshida, Shoji

    IPC分类号： G06T1/20

    CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3879 ,  G06F15/7832 ,  G06T1/20

    摘要： A graphic processing apparatus comprises a graphic processor (1) and a first memory (3, 4); wherein said graphic processor comprises a first port (103) for transmission or reception of data to and from said first memory (3, 4) in synchronism with a first clock (7), and a second port (102) for transmission or reception of data to and from a CPU (8) in synchronism with a second clock (13); and said graphic processing device is so constructed that data can be transmitted between said first memory (3, 4) and said CPU (8) by employing said first port (103) and said second port (102).

    摘要翻译： 一种图形处理装置，包括图形处理器（1）和第一存储器（3,4）; 其中所述图形处理器包括用于与第一时钟（7）同步地向所述第一存储器（3,4）发送数据或从所述第一存储器（3,4）接收数据的第一端口（103），以及用于发送或接收 与第二时钟（13）同步地向CPU（8）发送和来自CPU（8）的数据; 并且所述图形处理装置的结构使得通过使用所述第一端口（103）和所述第二端口（102）可以在所述第一存储器（3,4）和所述CPU（8）之间传输数据。

    Microprocessor, and graphics processing apparatus and method using the same
    7.
    发明公开
    Microprocessor, and graphics processing apparatus and method using the same 失效
    微处理器和与此微处理器的应用图形处理方法和装置。

    公开(公告)号：EP0395958A2

    公开(公告)日：1990-11-07

    申请号：EP90107548.1

    申请日：1990-04-20

    申请人： HITACHI, LTD.

    发明人： Yamada, Hiromichi ,  Fukushima, Tadashi ,  Matsuo, Shigeru ,  Miyamoto, Takashi ,  Komagawa, Toru ,  Yoshida, Shoji

    IPC分类号： G06F15/66

    CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3879 ,  G06F15/7832 ,  G06T1/20

    摘要： A microprocessor suitable for processing a large quantity of graphics data. Graphics processing apparatus and method using the microprocessor are also disclosed.
    The microprocessor (1) independent of a CPU has two ports (102, 103), and performs an instruction fetch and a data access or a memory access simultaneously to two me­mories (3, 10; 3, 4, 10) coupled through separate buses.
    In the graphics processing apparatus in which this microprocessor is employed, the graphics transfer between a system memory (10) and a frame memory (4) can be per­formed at higher speed.

    摘要翻译： 适合于处理的图形数据的大量的微处理器。 使用微处理器的图形处理装置和方法是如此游离缺失盘。 的CPU的微处理器（1）独立的具有两个端口（102，103）中，在指令执行获取和数据访问或同时的存储器访问两个存储器（3，10; 3，4，10）耦合以通过独立的总线 ， 在其中采用该微处理器的图形处理装置，系统存储器（10）和一个帧存储器（4）之间的图形转印可以在更高的速度进行。

    Parallel processor
    8.
    发明公开
    Parallel processor 失效
    并行处理器

    公开(公告)号：EP0347929A3

    公开(公告)日：1990-12-27

    申请号：EP89111465.4

    申请日：1989-06-23

    申请人： HITACHI, LTD.

    发明人： Yamada, Hiromichi ,  Katsura, Koyo

    IPC分类号： G06F15/173 ,  G06F13/40

    CPC分类号： G06F13/4022 ,  G06F15/17343

    摘要： A parallel processor comprises a plurality of proces­sing units (13) connected to each other via input/output ports (132). Each processing unit comprises: a local memory (131) for storing programs and data; a local bus for inputting/outputting the program and data to and from the memory and consisting of an address signal line, a data signal line, and a control signal line; a CPU (130) for reading the program from the local memory via the local bus as to process the program, for reading data needed to perform the processing from the memory via the local bus, and for making data which has been updated due to the processing to be stored again by the local memory through the local bus; a plurality of input/output ports (132) capable of connecting the local bus to a plurality of outside buses and needed for the CPU to input/output data to and from another memory of another processing unit or for another CPU of another processing unit to input/output data to and from this local memory; and bus switches for connec­ting two of the outside buses for the purpose of enabling data transfers between the CPU and the memory which are dis­posed on individual buses to be performed, wherein a main CPU (10) for setting program and data in the plural proces­sing units and for recovering data and the plural processing units are connected to the main CPU through at least one input/output port of the processing units.

    Parallel processor
    9.
    发明公开
    Parallel processor 失效
    平行球员考官。

    公开(公告)号：EP0347929A2

    公开(公告)日：1989-12-27

    申请号：EP89111465.4

    申请日：1989-06-23

    申请人： HITACHI, LTD.

    发明人： Yamada, Hiromichi ,  Katsura, Koyo

    IPC分类号： G06F15/173 ,  G06F13/40

    CPC分类号： G06F13/4022 ,  G06F15/17343

    摘要： A parallel processor comprises a plurality of proces­sing units (13) connected to each other via input/output ports (132). Each processing unit comprises: a local memory (131) for storing programs and data; a local bus for inputting/outputting the program and data to and from the memory and consisting of an address signal line, a data signal line, and a control signal line; a CPU (130) for reading the program from the local memory via the local bus as to process the program, for reading data needed to perform the processing from the memory via the local bus, and for making data which has been updated due to the processing to be stored again by the local memory through the local bus; a plurality of input/output ports (132) capable of connecting the local bus to a plurality of outside buses and needed for the CPU to input/output data to and from another memory of another processing unit or for another CPU of another processing unit to input/output data to and from this local memory; and bus switches for connec­ting two of the outside buses for the purpose of enabling data transfers between the CPU and the memory which are dis­posed on individual buses to be performed, wherein a main CPU (10) for setting program and data in the plural proces­sing units and for recovering data and the plural processing units are connected to the main CPU through at least one input/output port of the processing units.

    摘要翻译： 并行处理器包括经由输入/输出端口（132）彼此连接的多个处理单元（13）。 每个处理单元包括：用于存储程序和数据的本地存储器（131） 用于将程序和数据输入/输出到存储器并由地址信号线，数据信号线和控制信号线组成的本地总线; 用于经由本地总线从本地存储器读取程序以处理该程序的CPU（130），用于经由本地总线从存储器读取执行处理所需的数据，以及用于使数据由于 本地存储器通过本地总线再次存储处理; 多个输入/输出端口（132），其能够将本地总线连接到多个外部总线，并且所述CPU需要用于向另一个处理单元或另一个处理单元的另一个CPU的另一个存储器输入/输出数据 从本地存储器输入/输出数据; 以及用于连接两个外部总线的总线开关，用于实现在CPU和存储器之间的数据传输，这些数据传输设置在要执行的各个总线上，其中主CPU（10）用于设置多个处理单元中的程序和数据 并且用于恢复数据，并且多个处理单元通过处理单元的至少一个输入/输出端口连接到主CPU。