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    Memory module selection and reconfiguration apparatus in a data processing system
    2.
    发明公开
    Memory module selection and reconfiguration apparatus in a data processing system 失效
    存储器模块选择和重新配置在数据处理系统。

    公开(公告)号：EP0080626A2

    公开(公告)日：1983-06-08

    申请号：EP82110396.7

    申请日：1982-11-11

    申请人： HONEYWELL BULL ITALIA S.p.A.

    发明人： Mantellina, Calogero ,  Zanzottera, Daniele ,  Gelmetti, Marco

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0653

    摘要： Memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends during the sytem initialization to a central processing unit information related to the capacities of the constituting modules (Ml, M2, M3, M4).
    The central unit processes such information and provides through a channel (30) the memory with a set of information representative of the capacity of the first module (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory.
    This information set is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory.
    When the memory is addressed, a most significant address portion (BA 03 - 06) is compared at the same time by several comparators (33, 34, 35, 36), one for each register, with the content of the several registers.
    The comparison result signals in output from comparators are applied to a decoder (37) which, in function of such signals, generates signals selecting one among the several memory module.
    The module selection unit is carried out by means of simple and fast circuits so that the module selection time is very short.

    Digital timing unit
    4.
    发明公开
    Digital timing unit 失效
    Digitale Zeitsteuerungseinheit。

    公开(公告)号：EP0089596A1

    公开(公告)日：1983-09-28

    申请号：EP83102516.8

    申请日：1983-03-15

    申请人： HONEYWELL BULL ITALIA S.p.A.

    发明人： Mantellina, Calogero ,  Zanzottera, Daniele

    IPC分类号： G06F1/04 ,  H03K5/05

    CPC分类号： H03K5/1502 ,  G06F1/04 ,  H03K5/15066 ,  H03K5/15093

    摘要： Digital timing unit for timing data processing systems or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G 1 ) .... (G n ).
    The shift register, at first in a known status, is activated so that an electrical transition is shifted through the register cells and defines a timing cycle, at the end of which the register is set in a second known status.
    A feedback and control logic (3, 4, 5, 6, 7, 8, 9) allows to activate the register independently from its status and to keep it in the status occuring at the end of a timing cycle until a new start signal is received.
    The shift of the register is caused by timing pulses generated by an oscillator (1).
    The timing signals generated by the timing unit and present on the outputs of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.

    摘要翻译： 用于定时数据处理系统或其单元的数字定时单元，其中移位寄存器的输出信号被施加到多个独占或门（G1）....（Gn）。 首先处于已知状态的移位寄存器被激活，使得电转换通过寄存器单元移位并且定义定时周期，其结束时寄存器被设置在第二已知状态。 ...反馈和控制逻辑（3,4,5,6,7,8,9）允许独立于其状态激活寄存器，并使其保持在定时周期结束时发生的状态，直到 接收到一个新的启动信号。 ...寄存器的移位是由振荡器（1）产生的定时脉冲引起的。 ...由定时单元生成并存在于EXCLUSIVE OR的输出上的定时信号可以通过改变振荡器周期和/或EXCLUSIVE OR输入与输出之间的连接来修改长度 移位寄存器。