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    CALIBRATION-FREE LOCAL OSCILLATOR SIGNAL GENERATION FOR A HARMONIC-REJECTION MIXER
    1.
    发明公开
    CALIBRATION-FREE LOCAL OSCILLATOR SIGNAL GENERATION FOR A HARMONIC-REJECTION MIXER 有权
    校准本振信号的产生对于一个谐波抑制混频器

    公开(公告)号：EP2179504A2

    公开(公告)日：2010-04-28

    申请号：EP08751172.1

    申请日：2008-05-08

    申请人： NXP B.V.

    发明人： HE, Xin ,  BREKELMANS, Johannes, H., A.

    IPC分类号： H03D7/14

    CPC分类号： H03D7/14 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/1483 ,  H03D2200/0086 ,  H03K5/15093

    摘要： A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital localoscillator signalis presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signalat least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digitallocal oscillator signal with a predetermined signal having a static logical value. To compensate for phase errors the schematic topology of the first and the second waveform combiner circuit are arranged to be fully symmetrical to each other in that in the first waveform combiner, the circuit part for providing the function of the second waveform combiner is used as adummycircuit, and in the second waveform combiner, a circuit part for providing the function of the first waveform combiner is used as a dummy circuit. Accordingly, the sources for providing the multiple phases of the digital local oscillator signal see the same load, and hence required phase shift is guaranteed.

    Circuit de pilotage à l'usage de systèmes de simulation et d'entraînement au tir
    3.
    发明公开
    Circuit de pilotage à l'usage de systèmes de simulation et d'entraînement au tir 失效
    SteuerschaltungfürSimulations- und Schiessschulungssysteme。

    公开(公告)号：EP0384913A1

    公开(公告)日：1990-08-29

    申请号：EP90870029.7

    申请日：1990-02-21

    申请人： S.A. LEENTJENS-BOES

    发明人： Marganne, Henri

    IPC分类号： F41G3/26 ,  H03K5/15

    CPC分类号： H03K5/1502 ,  F41G3/265 ,  F41G3/2666 ,  H03K5/15093

    摘要： Le circuit est caractérisé par une utilisation de compteurs basse consommation pour générer les impulsions et par une définition du code par CI logiques après générateur(s) avec possibilité d'émission simultanée de deux codes synchrones ou non synchrones.

    摘要翻译： 该电路的特征在于使用低功耗计数器来产生脉冲，并且通过在发生器之后的IC逻辑单元定义代码，具有同时发射两个同步或非同步代码的可能性。

    Double clock frequency timing signal generator
    5.
    发明公开
    Double clock frequency timing signal generator 失效
    双时钟频率时序信号发生器

    公开(公告)号：EP0238874A3

    公开(公告)日：1989-02-01

    申请号：EP87102622.5

    申请日：1987-02-24

    申请人： International Business Machines Corporation

    发明人： Furman, Anatol

    IPC分类号： H03K5/15 ,  G06F1/04

    CPC分类号： H03K5/15093

    摘要： A clock generating circuit having at least one loop (40) of at least two stages (22, 30; 24, 32; 26, 34; 28, 36). Each stage consists of a pass transistor (22; 24; 26; 28) serially connected to an inverter (30; 32; 34; 36). An inverter (38) couples the end of the loop to its beginning. The gate electrodes of the transistors in the serially connected stages are controlled alternately by a true (CT) and a complemented (CC) clock signal. Preferably, there are two such loops (40; 44) operating in parallel but which include initialization circuitry (41, 42) that initializes the two loops to complementary values.

    Sequential selection circuits
    6.
    发明公开
    Sequential selection circuits 失效
    Sequentielle Auswahlschaltungen。

    公开(公告)号：EP0162605A1

    公开(公告)日：1985-11-27

    申请号：EP85302931.2

    申请日：1985-04-25

    申请人： SONY CORPORATION

    发明人： Shionoya,Toshio c/o Sony Corporation

    IPC分类号： G09G3/28 ,  H03K5/153 ,  H03K5/26 ,  H04N3/14

    CPC分类号： G09G3/296 ,  G09G3/293 ,  H03K5/15093 ,  H03K21/40

    摘要： @ A sequential selection circuit for selecting a series of circuits, elements, electrodes or other items over a long period, to activate them sequentially one by one for a short period, comprises a shift register (10) which has a number of shift stages corresponding to the total number that is to be selected for sequentially shifting a single input pulse in response to clock pulses (H) corresponding to the short period. A counter (11) counts the clock pulses (H) so as to generate a pulse output (Pi when a count reaches the total selection number. An input circuit (G1,G2.G3) generates an input pulse (V,) for the shift register (10) in accordance with the pulse output (P) from the counter (11) and a pulse (V) corresponding to the long period. A reset circuit (G1) resets the counter (11) in accordance with the clock pulse (H) and the pulse (V) corresponding to the long period. With such arrangement, when the pulse (V) corresponding to the long period is not generated, the counter (11) will not operate and an effective input pulse (V,) to the shift register (10) will not be generated. Therefore, the shift register (10) will not sequentially read erroneous inputs and a plurality of shift stage outputs will not be generated at the same time. In this manner, the selected circuits, elements, electrodes or other items and drive circuitry and a power supply will be prevented from being damaged.

    摘要翻译： 一种用于长时间选择一系列电路，元件，电极或其他物品的顺序选择电路，用于在短时间内逐个激活它们，包括移位寄存器（10），其具有对应于 响应于对应于短周期的时钟脉冲（H），顺序移位单个输入脉冲而被选择的总数。 当计数达到总选择数时，计数器（11）对时钟脉冲（H）进行计数，以产生脉冲输出（P）。 输入电路（G1，G2，G3）根据来自计数器（11）的脉冲输出（P）和对应于长周期的脉冲（V）产生用于移位寄存器（10）的输入脉冲（V1） 。 复位电路（G1）根据时钟脉冲（H）和对应于长周期的脉冲（V）来重置计数器（11）。 通过这样的配置，当不产生对应于长周期的脉冲（V）时，计数器（11）将不工作，并且不会产生对移位寄存器（10）的有效输入脉冲（V1）。 因此，移位寄存器（10）不会顺序地读取错误的输入，并且不会同时产生多个移位级输出。 以这种方式，将防止所选择的电路，元件，电极或其它物品以及驱动电路和电源被损坏。

    Timing circuit
    8.
    发明公开
    Timing circuit 失效
    Zeitschaltungsanordnung

    公开(公告)号：EP0701325A1

    公开(公告)日：1996-03-13

    申请号：EP95305826.0

    申请日：1995-08-21

    申请人： SGS-THOMSON MICROELECTRONICS LTD.

    发明人： Beat, Robert

    IPC分类号： H03K5/15 ,  H03K23/54 ,  H03K23/66

    CPC分类号： H03K5/15093 ,  H03K23/54 ,  H03K23/665

    摘要： The current invention provides a timer circuit for timing a plurality of time periods, having: a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values.
    A first timing signal generator generates a first timing signal to indicate the expiry of a first time period by detecting the first occurrence of the second logic value (0) in a subset of the set of logic states at the set of state outputs;
       a second timing signal generator generates a second timing signal to indicate the expiry of a second time period by detecting a predetermined combination of logic values at the set of state outputs.

    摘要翻译： 本发明提供了一种用于定时多个时间段的定时器电路，具有：用于接收定时脉冲的定时脉冲输入; 一组状态输出处于一组逻辑状态，每个逻辑状态采用两个逻辑值中的一个，逻辑状态集合的逻辑值在每个定时脉冲处改变; 多个定时输出，每个定时输出在预定时间段期满时提供信号; 以及用于复位定时电路并且用于定义初始逻辑状态集合的复位信号。 逻辑状态集合遵循逻辑值集合的第一序列，从逻辑值的初始集合开始，其中除了至少一个逻辑状态之外，每个集合内的所有逻辑状态都处于第一逻辑值（1），其中 处于第二逻辑值（0）的情况下，在逻辑值集合的第一序列内的每组逻辑值中承载异常状态的不同状态输出。 第一定时信号发生器通过检测在该组状态输出处的该组逻辑状态的子集中的第二逻辑值（0）的第一次出现来产生第一定时信号以指示第一时间段的到期; 第二定时信号发生器通过在所述一组状态输出处检测逻辑值的预定组合来产生第二定时信号以指示第二时间段的期满。

    Logic circuit
    10.
    发明公开
    Logic circuit 失效
    Logikschaltung。

    公开(公告)号：EP0524712A2

    公开(公告)日：1993-01-27

    申请号：EP92301172.0

    申请日：1992-02-13

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Nakao, Tomoaki

    IPC分类号： H03K19/00 ,  H03K5/15 ,  G11C19/28

    CPC分类号： H03K5/15093

    摘要： A logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external, includes at least one synchronous flip-flop (31, 32, 33, 34) being synchronized with the clock signal, the flip-flop for latching the input signal, and a unit (51, 52, 53, 54, 61, 62, 63, 64) for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.

    摘要翻译： 用于根据从外部发送的时钟信号输出对应于输入信号的信号的逻辑电路包括与时钟信号同步的至少一个同步触发器（31,32,33,34），所述触发器用于 锁存输入信号，以及单元（51,52,53,54,61,62,63,64），用于基于输入信号的输出信号的逻辑电平之间的差来控制对触发器的时钟信号的输入 触发器和触发器新锁存的输入信号。