摘要:
Embodiments of this application provide a packet processing method and apparatus, a communications device, and a switching circuit. The method includes: receiving, by a first device, a packet from a second device; determining, by the first device, a first queue buffer used to store the packet; determining, by the first device, a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer; and processing, by the first device, the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet. In the embodiments of this application, differentiated packet discarding is implemented.
摘要:
The invention relates to a scheduling device (200) for receiving a set of requests (202) and providing a set of grants (204) to the set of requests (202), the scheduling device (200) comprising: a lookup vector prepare unit (203) configured to provide a lookup vector prepared set of requests (208) depending on the set of requests (202) and a selection mask (210) and to provide a set of acknowledgements (212) to the set of requests (202); and a prefix forest unit (205) coupled to the lookup vector prepare unit (203), wherein the prefix forest unit (205) is configured to provide the set of grants (204) as a function of the lookup vector prepared set of requests (208) and to provide the selection mask (210) based on the set of grants (204).
摘要:
The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.