公开(公告)号：EP4451566A1

公开(公告)日：2024-10-23

申请号：EP24168323.4

申请日：2024-04-03

申请人： Hamilton Sundstrand Corporation

发明人： MADATHIKANDAM, Rajesh ,  HILL, Robin David ,  VIJAY, Ashish ,  POTTER, Stephen ,  KRISHNA, Rajeeva ,  THANGAVEL, Anitha

IPC分类号： H03K19/1776

摘要： A bus controller-based page memory programmable logic device (PLD) architecture (100) includes a plurality of PLD modules (102a-102n) and a bus controller (104) in signal communication with the plurality of PLD modules via a universal bus interface (106a, 106b). Each PLD module include a PLD memory unit (112) configured to store first data. The bus controller includes bus memory unit (122) configured to store second data and includes a bus controller engine (120) configured to sequentially execute a set of bus controller instructions. One or both of the first data and the second data is transferred between the bus controller and a target PLD module among the plurality of PLD modules in response to sequentially executing the set of bus controller instructions.