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    SCALABLE AND MODULAR BUS CONTROLLER INCLUDING PAGE MEMORY PLD ARCHITECTURE
    1.
    发明公开
    SCALABLE AND MODULAR BUS CONTROLLER INCLUDING PAGE MEMORY PLD ARCHITECTURE 审中-公开

    公开(公告)号：EP4451566A1

    公开(公告)日：2024-10-23

    申请号：EP24168323.4

    申请日：2024-04-03

    申请人： Hamilton Sundstrand Corporation

    发明人： MADATHIKANDAM, Rajesh ,  HILL, Robin David ,  VIJAY, Ashish ,  POTTER, Stephen ,  KRISHNA, Rajeeva ,  THANGAVEL, Anitha

    IPC分类号： H03K19/1776

    摘要： A bus controller-based page memory programmable logic device (PLD) architecture (100) includes a plurality of PLD modules (102a-102n) and a bus controller (104) in signal communication with the plurality of PLD modules via a universal bus interface (106a, 106b). Each PLD module include a PLD memory unit (112) configured to store first data. The bus controller includes bus memory unit (122) configured to store second data and includes a bus controller engine (120) configured to sequentially execute a set of bus controller instructions. One or both of the first data and the second data is transferred between the bus controller and a target PLD module among the plurality of PLD modules in response to sequentially executing the set of bus controller instructions.

    HYBRID MICROPROCESSOR AND PROGRAMMABLE LOGIC DEVICE (PLD)- BASED ARCHITECTURE INCLUDING INTER PROCESSOR COMMUNICATION
    2.
    发明公开
    HYBRID MICROPROCESSOR AND PROGRAMMABLE LOGIC DEVICE (PLD)- BASED ARCHITECTURE INCLUDING INTER PROCESSOR COMMUNICATION 审中-公开

    公开(公告)号：EP4456433A1

    公开(公告)日：2024-10-30

    申请号：EP24168451.3

    申请日：2024-04-04

    申请人： Hamilton Sundstrand Corporation

    发明人： MADATHIKANDAM, Rajesh ,  HILL, Robin ,  POTTER, Stephen ,  VIJAY, Ashish ,  KRISHNA, Rajeeva ,  THANGAVEL, Anitha

    IPC分类号： H03K19/17732 ,  G06F15/78

    摘要： A microprocessor-PLD hybrid architecture includes an IPC microprocessor (102) and a PLD (150) in signal communication with the IPC microprocessor (102) via an IPC interface (104). The IPC microprocessor (102) outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules (154a-154n) that store data and a bus controller (152). The bus controller (152) communicates with the plurality of PLD modules (154a-154n) via a plurality of PLD interfaces (170) and is configured to sequentially execute a set of bus controller instructions (166). The bus controller (152) reads data from a target PLD module from among the plurality of PLD modules (154a-154n) in response to receiving the data read command, and transfers the data to the IPC microprocessor (102). The bus controller (152) receives data from the IPC microprocessor (102) and stores the data in a target PLD module from among the plurality of PLD modules (154a-154n) in response to receiving the data write command.