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公开(公告)号：EP0453158A2
公开(公告)日：1991-10-23
申请号：EP91303128.2
申请日：1991-04-09
CPC分类号： G06G7/184
摘要： A switched-current integrator circuit (50) employs track-and-hold circuits (52,54) in which the gates of the current mirror FET switches (M1,M2) are connected together to form a common gate node (58) to double the effective holding capacitance. Additionally, the common gate node (58) is coupled to the input terminal (16) through a CMOS switch (62,64) so that parasitic clock feed-through is essentially cancelled to minimize DC offset voltages (V1,V3 in FIG. 4).
摘要翻译： 开关电流积分器电路（50）采用跟踪和保持电路（52,54），其中电流镜FET开关（M1，M2）的栅极连接在一起，以形成公共栅极节点（58），以加倍 有效保持电容。 此外，公共栅极节点（58）通过CMOS开关（62,64）耦合到输入端子（16），使得基本上消除寄生时钟馈通以最小化DC偏移电压（图4中的V1，V3） ）。
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2.发明公开Energy control circuit for a thermal inkjet printhead 失效Energiesteuerungsschaltungfürthermischen Tintenstrahldruckkopf。
公开(公告)号：EP0499373A2
公开(公告)日：1992-08-19
申请号：EP92300644.9
申请日：1992-01-24
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0455 , B41J2/0457 , B41J2/0458 , B41J2/355
摘要： A circuit (10) for controlling the energy delivered to a heater resistor (RH) of a thermal inkjet printhead. The circuit includes a decoder (12) for receiving an address for the heater resistor in a multiplexed environment. When the heater resistor is addressed, the output of the decoder is level shifted through a pair of inverters (24, 26) and transmitted to the gate of a PMOS driver (34) that delivers the energy to the heater resistor (RH). The PMOS driver (34) responds to the voltage level of the adjacent inverter output in setting the level of the driver output voltage that is applied to the resistor (RH). Feedback circuitry in the form of an analog (32) or digital (42) comparator compares the driver output voltage (VOUT) against a reference voltage (VREF). The comparator's output signal is fed back through the level shifter (16) as the inverter output that is applied to the gate of the PMOS driver (34). The inverter output adjusts the driver output voltage so as to maintain the voltage (Vo) across the heater resistor at a level that delivers a desired amount of energy to the heater resistor (RH).
摘要翻译： 一种用于控制传递到热喷墨打印头的加热电阻器（RH）的能量的电路（10）。 该电路包括用于在复用环境中接收加热电阻器的地址的解码器（12）。 当加热电阻器被寻址时，解码器的输出通过一对反相器（24,26）进行电平移位，并被传送到将能量传递给加热电阻器（RH）的PMOS驱动器（34）的栅极。 在设定施加到电阻器（RH）的驱动器输出电压的电平时，PMOS驱动器（34）响应相邻的反相器输出的电压电平。 以模拟（32）或数字（42）比较器形式的反馈电路将驱动器输出电压（VOUT）与参考电压（VREF）进行比较。 比较器的输出信号通过电平移位器（16）作为施加到PMOS驱动器（34）的栅极的反相器输出反馈。 变频器输出调整驱动器输出电压，以便将加热电阻器两端的电压（Vo）保持在向加热电阻（RH）传递所需能量的水平。
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公开(公告)号：EP0499373B1
公开(公告)日：1996-10-09
申请号：EP92300644.9
申请日：1992-01-24
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0455 , B41J2/0457 , B41J2/0458 , B41J2/355
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公开(公告)号：EP0499373A3
公开(公告)日：1992-08-26
申请号：EP92300644.9
申请日：1992-01-24
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0455 , B41J2/0457 , B41J2/0458 , B41J2/355
摘要： A circuit (10) for controlling the energy delivered to a heater resistor (RH) of a thermal inkjet printhead. The circuit includes a decoder (12) for receiving an address for the heater resistor in a multiplexed environment. When the heater resistor is addressed, the output of the decoder is level shifted through a pair of inverters (24, 26) and transmitted to the gate of a PMOS driver (34) that delivers the energy to the heater resistor (RH). The PMOS driver (34) responds to the voltage level of the adjacent inverter output in setting the level of the driver output voltage that is applied to the resistor (RH). Feedback circuitry in the form of an analog (32) or digital (42) comparator compares the driver output voltage (VOUT) against a reference voltage (VREF). The comparator's output signal is fed back through the level shifter (16) as the inverter output that is applied to the gate of the PMOS driver (34). The inverter output adjusts the driver output voltage so as to maintain the voltage (Vo) across the heater resistor at a level that delivers a desired amount of energy to the heater resistor (RH).
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公开(公告)号：EP0453158A3
公开(公告)日：1992-04-01
申请号：EP91303128.2
申请日：1991-04-09
CPC分类号： G06G7/184
摘要： A switched-current integrator circuit (50) employs track-and-hold circuits (52,54) in which the gates of the current mirror FET switches (M1,M2) are connected together to form a common gate node (58) to double the effective holding capacitance. Additionally, the common gate node (58) is coupled to the input terminal (16) through a CMOS switch (62,64) so that parasitic clock feed-through is essentially cancelled to minimize DC offset voltages (V1,V3 in FIG. 4).
摘要翻译： 开关电流积分器电路（50）采用跟踪和保持电路（52,54），其中电流镜FET开关（M1，M2）的栅极连接在一起，以形成公共栅极节点（58），以加倍 有效保持电容。 此外，公共栅极节点（58）通过CMOS开关（62,64）耦合到输入端子（16），使得基本上消除寄生时钟馈通以最小化DC偏移电压（图4中的V1，V3） ）。
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