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    Method and system for pulse signal transmission
    1.
    发明公开
    Method and system for pulse signal transmission 失效
    的方法和系统脉冲信号传输。

    公开(公告)号：EP0089467A1

    公开(公告)日：1983-09-28

    申请号：EP83100759.6

    申请日：1983-01-27

    申请人： Hitachi, Ltd.

    发明人： Yoshine, Hiroki ,  Takasaki, Yoshitaka ,  Tkahashi, Yasushi ,  Yamada, Mitsuo ,  Nagano, Katsuyuki

    IPC分类号： H04L25/49

    CPC分类号： H04L25/4906 ,  H04L25/49

    摘要： A two-level alternate mark inversion signal transmission system wherein binary pulses of "1" and "0" are converted into a pulse signal in which one has its polarity inverted at a period T and the other at a period T:2, and the converted signal is transmitted. In order to facilitate an automatic gain control and the extraction of a timing signal on a receiving side even when the zero binary pulses have successively arisen; on a transmitting side, the alternate mark inversion signal is converted into a specified code (zero substitution) signal when the zero binary pulses have succeeded, while on the receiving side, a received signal is subjected to duobinary shaping, whereupon the zero substitution part is decided for removal by utilizing the rules of the zero substitution and the alternate mark inversion signal.

    Time domain multiplexer
    2.
    发明公开
    Time domain multiplexer 失效
    Zeitmultiplexer。

    公开(公告)号：EP0073043A1

    公开(公告)日：1983-03-02

    申请号：EP82107654.4

    申请日：1982-08-20

    申请人： Hitachi, Ltd.

    发明人： Nagano, Katsuyuki ,  Takahashi, Yasushi ,  Takasaki, Yoshitaka ,  Tanaka, Mitsuo

    IPC分类号： H04L5/22 ,  H04J3/16

    CPC分类号： H04J3/1629 ,  H04L5/22

    摘要： In order to enhance the general-purposeness of a time domain multiplexer for digital channel-signals of unequal bit rates, the time domain multiplexer is constructed of a plurality of channel units (7) which provide information signals and bit rate signals of input channel signals, a plurality of logic circuits (37 ... 45) which multiplex the information signals from the channel units (7), and a control circuit (46 ... 50) which selects and combines the logic circuits (37 ... 45) in accordance with the bit rate signal so as to construct a multiplexer conforming with the bit rate.