公开(公告)号：EP0436958A3

公开(公告)日：1992-12-09

申请号：EP90125766.7

申请日：1990-12-28

申请人： HITACHI, LTD.

发明人： Takahashi, Yasushi ,  Amada, Eiichi ,  Ando, Kimiaki ,  Miyata, Masanori

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/0605 ,  H04Q11/0001 ,  H04Q11/0066

摘要： A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of an signal adder circuit (2) for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit (12) for separating and out-putting the time series cell signals. The dummy signal composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the above-mentioned cell signal processing circuit as an optical switch array (8) is also provided which includes a photoelectric converter (9) for converting the time series optical cell signal to an electric signal, a clock recovery circuit (13) for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit (14) for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit (11) for decision the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention has a simple circuit arrangement which is not influenced by data loss and jitter.

公开(公告)号：EP0481349A2

公开(公告)日：1992-04-22

申请号：EP91117242.7

申请日：1991-10-09

申请人： HITACHI, LTD.

发明人： Takahashi, Yasushi ,  Itoh, Hiroyuki

IPC分类号： G06F1/10

CPC分类号： H04L7/0075 ,  G06F1/06 ,  G06F1/105 ,  H04L7/0337

摘要： A logic processing apparatus comprises a plurality of integrated circuits (6-1 - 6-n), a multi-phase clock generator (5) for distributing clock signals having different phases from one another to the respective integrated circuits (6-1 - 6-n), and a package (20), for air tight sealing the multi-phase clock generator (5) and the plurality of integrated circuits (6-1 - 6-n), which has an optical signal transmissible window for transmitting the master clock to the multi-phase clock generator (5) through the optical transmitting line (4).

摘要翻译： 逻辑处理装置包括多个集成电路（6-1至6-n），多相时钟发生器（5），用于将具有彼此不同相位的时钟信号分配给各个集成电路（6-1-6） -n）和用于气密密封多相时钟发生器（5）和多个集成电路（6-1-6-n）的封装（20），其具有用于传输 主时钟通过光传输线（4）发送到多相时钟发生器（5）。

公开(公告)号：EP0455108A3

公开(公告)日：1993-08-04

申请号：EP91106537.3

申请日：1991-04-23

申请人： HITACHI, LTD.

发明人： Takahashi, Yasushi

IPC分类号： H04Q11/00

CPC分类号： H04Q11/0001 ,  H04J14/0227 ,  H04J14/0246 ,  H04J14/0283

摘要： A crossconnect unit, comprising: a unit for inputting a plurality of coherent signals having a sub-signal added to a main signal (24) after said sub-signal has been modulated by one of a group of modulation methods including a frequency modulation, a phase modulation, an intensity modulation and an amplitude modulation which are different from those applied to said main signal; a wavelength filter (1) for extracting a desired signal from said plurality of coherent signals; a destination decoder (3) for detecting said sub-signal from said extracted signal and extracting destination information (22); and means (4) for setting a signal path for said extracted signal based on said destination information.

摘要翻译： 一种交叉连接单元，包括：用于在所述子信号已经通过包括频率调制的一组调制方法中的一种调制之后，输入具有添加到主信号（24）的子信号的多个相干信号的单元， 相位调制，强度调制和幅度调制不同于施加到所述主信号的调制; 用于从所述多个相干信号中提取所需信号的波长滤波器（1）; 目的地解码器（3），用于从所述提取的信号中检测所述子信号并提取目的地信息（22）; 以及用于基于所述目的地信息设置所述提取信号的信号路径的装置（4）。

公开(公告)号：EP0475016A3

公开(公告)日：1992-09-09

申请号：EP91111787.7

申请日：1991-07-15

申请人： HITACHI, LTD.

发明人： Takahashi, Yasushi ,  Tanaka, Katuya, Hitachi Daiyon Kyoshinryo A309

IPC分类号： H04J14/02

CPC分类号： H04J14/0204 ,  H04J14/0201 ,  H04J14/0205 ,  H04J14/0206

摘要： A wavelength separator in a wavelength-multiplexed optical network system uses a wavelength demultiplexer (2) having optical elements having wavelength selectivity arranged in tandem to directly demultiplex light signals by wavelength without distributing all input light signals. When a node device (A-E, M) is down, a power supply fails or a control signal is not issued, the received light signals are not demultiplexed but propagated through an optical wave-guide (2-1).

公开(公告)号：EP0475016A2

公开(公告)日：1992-03-18

申请号：EP91111787.7

申请日：1991-07-15

申请人： HITACHI, LTD.

发明人： Takahashi, Yasushi ,  Tanaka, Katuya, Hitachi Daiyon Kyoshinryo A309

IPC分类号： H04J14/02

CPC分类号： H04J14/0204 ,  H04J14/0201 ,  H04J14/0205 ,  H04J14/0206

摘要： A wavelength separator in a wavelength-multiplexed optical network system uses a wavelength demultiplexer (2) having optical elements having wavelength selectivity arranged in tandem to directly demultiplex light signals by wavelength without distributing all input light signals. When a node device (A-E, M) is down, a power supply fails or a control signal is not issued, the received light signals are not demultiplexed but propagated through an optical wave-guide (2-1).

摘要翻译： 波分复用光网络系统中的波长分离器使用具有串联布置的具有波长选择性的光学元件的波长解复用器（2），而不分散所有输入光信号而直接对光信号进行解调。 当节点设备（A-E，M）关闭时，电源故障或不发出控制信号，接收的光信号不被解复用，而是通过光波导（2-1）传播。

公开(公告)号：EP0073043B1

公开(公告)日：1986-07-23

申请号：EP82107654.4

申请日：1982-08-20

申请人： Hitachi, Ltd.

发明人： Nagano, Katsuyuki ,  Takahashi, Yasushi ,  Takasaki, Yoshitaka ,  Tanaka, Mitsuo

IPC分类号： H04L5/22 ,  H04J3/16

CPC分类号： H04J3/1629 ,  H04L5/22

公开(公告)号：EP0892409B1

公开(公告)日：2004-04-28

申请号：EP98305701.9

申请日：1998-07-16

申请人： TEXAS INSTRUMENTS INCORPORATED ,  Hitachi, Ltd.

发明人： Hira, Masayuki ,  Sukegawa, Shunichi ,  Bessho, Shinji ,  Takahashi, Yasushi ,  Arai, Koji ,  Takahashi, Tsutomu ,  Takahashi, Tsugio

IPC分类号： G11C11/409 ,  G11C7/06

CPC分类号： G11C7/065 ,  G11C11/4091

公开(公告)号：EP0436958A2

公开(公告)日：1991-07-17

申请号：EP90125766.7

申请日：1990-12-28

申请人： HITACHI, LTD.

发明人： Takahashi, Yasushi ,  Amada, Eiichi ,  Ando, Kimiaki ,  Miyata, Masanori

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/0605 ,  H04Q11/0001 ,  H04Q11/0066

摘要： A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of an signal adder circuit (2) for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit (12) for separating and out-putting the time series cell signals. The dummy signal composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the above-mentioned cell signal processing circuit as an optical switch array (8) is also provided which includes a photoelectric converter (9) for converting the time series optical cell signal to an electric signal, a clock recovery circuit (13) for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit (14) for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit (11) for decision the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention has a simple circuit arrangement which is not influenced by data loss and jitter.

摘要翻译： 提供一种能够精确地提取定时信号和单元同步信号的单元信号处理电路。 单元信号处理电路主要由信号加法电路（2）构成，信号加法电路（2）将包含直流平衡状态的位信号的虚拟信号与各输入的时间序列单元信号的端部相加，分离电路（12） 分离并输出时间序列信号。 由相同数量的位“0”和“1”组成的虚拟信号以时间序列单元的形式被添加到输入信号中，使得信号单元在虚拟信号中在位“0”的时间被交换。 还提供了一种使用上述单元信号处理电路作为光开关阵列（8）的光开关装置，其包括用于将时间序列光信号信号转换为电信号的光电转换器（9），时钟恢复电路 13），用于从光电转换器的输出提取时钟信号，用于从光电转换器的输出提取单元同步信号的单元同步电路（14）和用于判定光电转换器的输出的判定电路（11） 转换器通过使用时钟信号。 本发明的光开关装置具有简单的电路布置，不受数据丢失和抖动的影响。

公开(公告)号：EP0892409A3

公开(公告)日：1999-07-28

申请号：EP98305701.9

申请日：1998-07-16

申请人： TEXAS INSTRUMENTS INCORPORATED ,  Hitachi, Ltd.

发明人： Hira, Masayuki ,  Sukegawa, Shunichi ,  Bessho, Shinji ,  Takahashi, Yasushi ,  Arai, Koji ,  Takahashi, Tsutomu ,  Takahashi, Tsugio

IPC分类号： G11C11/409 ,  G11C7/06

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： Controlling the timing for the overdrive of the sense amplifiers in response to the conductor length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines. The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the conductor length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the conductor between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

摘要翻译： 响应于读出放大器与电源电压供应节点之间的导体长度来控制读出放大器的过驱动的定时，并且通过防止位线的过度过驱动来设计功耗的降低。 根据用于驱动读出放大器的电源的供电节点CT0，CT1，CT2之间的导体长度和每个读出放大器组SB0至SB16之间的导体长度来控制到每个读出放大器组的电源电压的供应定时， 并且由于到近端的读出放大器组SB0的过驱动电压的供给时间被设定得短，并且过驱动电压的供给时间随着朝向远端而被连续设定得更长，所以感测延迟源于电压 补偿在供电节点和读出放大器组之间的导体中产生的压降，可以实现远端和近端的位线的过驱动的均匀性，读出放大器组（存储单元 垫）可以避免，并且进一步地，可以实现功耗的降低。

公开(公告)号：EP0892409A2

公开(公告)日：1999-01-20

申请号：EP98305701.9

申请日：1998-07-16

申请人： TEXAS INSTRUMENTS INCORPORATED ,  Hitachi, Ltd.

发明人： Hira, Masayuki ,  Sukegawa, Shunichi ,  Bessho, Shinji ,  Takahashi, Yasushi ,  Arai, Koji ,  Takahashi, Tsutomu ,  Takahashi, Tsugio

IPC分类号： G11C11/409 ,  G11C7/06

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： Controlling the timing for the overdrive of the sense amplifiers in response to the conductor length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.
The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the conductor length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the conductor between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.