公开(公告)号：EP1016968B1

公开(公告)日：2002-09-11

申请号：EP00100479.5

申请日：1994-10-12

申请人： Hitachi, Ltd.

发明人： Kanekawa, Nobuyasu ,  Shoji, Suzuki ,  Sato, Yoshimichi ,  Tashiro, Korefumi ,  Keisuke,Bekki ,  Sato, Hiroshi ,  Nohmi, Makoto ,  Ohtsuji, Shinya

IPC分类号： G06F11/16

CPC分类号： G05B9/03 ,  G06F11/0763 ,  G06F11/0796 ,  G06F11/085 ,  G06F11/1608 ,  G06F11/1695 ,  G06F11/188 ,  G06F11/2215

摘要： The present invention relates to a self-checking circuit and a method of its configuration. More particularly, it concerns a self-checking circuit useful for highly reliable system configuration. As for a logic circuit having error detection function that has function blocks (110,111) of feeding out a plurality of signals (430,431) at least duplexed, compares the output signals of the function blocks, and detects an error on the basis of results of the comparison, wherein the operations of the function blocks are delayed.