公开(公告)号：EP3311273A1

公开(公告)日：2018-04-25

申请号：EP16721152.3

申请日：2016-05-04

申请人： Robert Bosch GmbH

发明人： EMPERLE, Alexander ,  PLETINCKX, Jo ,  SCHEUING, Jan

IPC分类号： G06F9/48 ,  G06F9/32 ,  G06F11/30 ,  G06F13/24

CPC分类号： G06F9/4831 ,  G06F9/321 ,  G06F9/327 ,  G06F9/4812 ,  G06F11/1608 ,  G06F11/1637 ,  G06F11/3024 ,  G06F13/24

摘要： The invention relates to a method for protecting a program counter structure (102) of a processor system (104) in the case of an interrupt request (106). The processor system (104) comprises at least the program counter structure (102), an interrupt control device (108) and a memory (110). The interrupt control device (108) is designed to respond to the interrupt request (106) by providing the program counter structure (102) with an address (112) associated with the interrupt request (106). The program counter structure (102) is designed to output an address (352) to the memory (110) via a memory interface (114). The method (400) has a read-in step, a comparison step and a provision step. In the read-in step, the address (352) is read in from the memory interface (104). In the comparison step (404), this address (352) is compared with a desired address (120) associated with the interrupt request (106) in order to obtain a comparison result (126). In the provision step, a match signal (124) is provided using the comparison result (126). The latter can also be used for monitoring the handling of interrupt requests. For example, it can be used for monitoring observance of the priority of these interrupt requests or as part of monitoring of the correct execution of the interrupt routine associated with the interrupt request (interrupt service routine).

公开(公告)号：EP3273353A1

公开(公告)日：2018-01-24

申请号：EP15886231.8

申请日：2015-03-20

申请人： Renesas Electronics Corporation

发明人： YUYAMA, Yoichi ,  TAKADA, Kiwamu

IPC分类号： G06F11/18

CPC分类号： G06F1/06 ,  G06F11/1608 ,  G06F11/1625 ,  G06F11/1641 ,  G06F11/1675 ,  G06F11/1695 ,  G06F13/4213 ,  G06F13/4226 ,  G06F13/4239 ,  H04L12/5601 ,  H04L2012/566

摘要： In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

摘要翻译： 在包括分别复制在彼此异步的两个时钟域中的两组电路对的数据处理设备中，在两组电路对之间提供传送有效载荷信号的异步传送电路。 异步传送电路包括两组分别连接到两组电路对的桥接电路，并且在接收侧异步传送有效载荷信号和指示有效载荷信号稳定的时间的控制信号。 两组桥电路和有效载荷信号可以被复制，但是控制信号不被复制，并且所接收的有效载荷信号被用于定时控制以向该对复制电路提供预期的相同时间差。 这使异步时钟域中复制的电路之间的异步传输成为可能。

公开(公告)号：EP2824572A1

公开(公告)日：2015-01-14

申请号：EP13176326.0

申请日：2013-07-12

申请人： Thales Deutschland GmbH

发明人： Ilie, Gabriel Cristian ,  Maringer, Daniel ,  Niedermayer, Klaus ,  Grund, Daniel

IPC分类号： G06F11/16 ,  G06F11/18

CPC分类号： G06F11/1608 ,  G06F11/1641 ,  G06F11/184

摘要： The invention concerns a fail-safe device for a data output system, the device comprising at least one memory unit (4a, 4b) for storing a set of first telegrams and a set of second telegrams, at least one input processor (1a, 1b) for selecting one of the stored first telegrams and one of the stored second telegrams; and an XOR-device (5) with a first input channel (A) for transmitting the selected first telegram, a second input channel (B) for transmitting the selected second telegram, and with an output channel (O) for transmitting a third telegram, the third telegram being the result of an XOR-operation of the first and the second telegram. Thus a composite fail safe system for Data Output Systems is provided with a simple structure.

摘要翻译： 本发明涉及一种用于数据输出系统的故障安全装置，该装置包括用于存储一组第一电报和一组第二电报的至少一个存储单元（4a，4b），至少一个输入处理器（1a，1b） ），用于选择所存储的第一电报之一和存储的第二电报之一; 以及具有用于发送所选择的第一电报的第一输入通道（A）的XOR装置（5），用于发送所选择的第二电报的第二输入通道（B）和用于发送第三电报的输出通道（O） ，第三个电报是第一个和第二个电报的异或运算的结果。 因此，数据输出系统的复合故障安全系统具有简单的结构。

公开(公告)号：EP2241952A1

公开(公告)日：2010-10-20

申请号：EP09005484.2

申请日：2009-04-17

申请人： Siemens Aktiengesellschaft

发明人： Schenk, Andreas ,  Walter, Markus

IPC分类号： G05B23/02 ,  G06F1/14

CPC分类号： G06F11/1604 ,  G05B19/0428 ,  G06F11/1608

摘要： Verfahren zur Überprüfung einer Datenverarbeitungseinrichtung auf die Eignung zur Durchführung fehlersicherer Automatisierungsabläufe
Die vorliegende Erfindung betrifft ein Verfahren zur Überprüfung einer Datenverarbeitungseinrichtung (100), insbesondere einer Automatisierungseinrichtung (100) oder eines Computers (100), auf die Eignung zur Durchführung fehlersicherer Automatisierungs-Abläufe,
wobei die Datenverarbeitungseinrichtung (100) eine erste (138) und eine zweite Zeitbasis (136) aufweist, und
wobei das Verfahren die folgenden Schritte umfasst:
- Ermittlung eines ersten Zeitwerts der ersten Zeitbasis (138) nach dem Ablauf einer Zeitspanne der Länge T,
- Ermittlung eines zweiten Zeitwerts der zweiten Zeitbasis (136) nach dem Ablauf einer Zeitspanne der Länge T,
- Bestimmung einer Abweichung zwischen dem ersten und dem zweiten Zeitwert,
- Auslösen einer Störungsmaßnahme, wenn die Abweichung einen vorgegebenen oder vorgebbaren Grenzwert unterschreitet, insbesondere unterschreitet oder erreicht.

摘要翻译： 所述方法涉及确定特定开采长度的时间期满之后的一个时基值。 的另一个时基AnotherValue类似长度的时间期满后，确定开采。 在前者和后者值之间的偏差是确定的开采。 甲故障动作时获得偏差低于预先确定的或预先设定的阈值。 因此独立权利要求中包括了以下内容：（1）数据处理装置; （2）上的适宜性验证的数据处理装置执行故障安全自动化过程的程序元件; 和（3）的计算机可读存储介质中。

公开(公告)号：EP1949236B1

公开(公告)日：2009-07-22

申请号：EP06819082.6

申请日：2006-10-16

申请人： International Business Machines Corporation

发明人： CONDORELLI, Vincenzo ,  DEWKETT, Thomas ,  HOCKER, Michael ,  VISEGRADY, Tamas

IPC分类号： G06F11/16

CPC分类号： G06F11/1608 ,  G06F11/1616 ,  G06F11/1625

摘要： In a communications channel coupled to multiple duplicated subsystems, a method, interposer and program product are provided for verifying integrity of subsystem responses. Within the communications channel, a first checksum is calculated with receipt of a first response from a first subsystem responsive to a common request, and a second checksum is calculated for a second response of a second subsystem received responsive to the common request. The first checksum and the second checksum are compared, and if matching, only one of the first response and the second response is forwarded from the communications channel as the response to the common request, with the other of the first response and the second response being discarded by the communications channel.

公开(公告)号：EP1604281A1

公开(公告)日：2005-12-14

申请号：EP04721222.0

申请日：2004-03-17

申请人： ARM Limited ,  University of Michigan

发明人： AUSTIN, Todd, Michael ,  BLAAUW, David, Theodore ,  MUDGE, Trevor, Nigel ,  FLAUTNER, Krisztian

IPC分类号： G06F11/00

CPC分类号： G06F11/1695 ,  G06F9/3861 ,  G06F9/3869 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit includes a plurality of processing stages each including processing logic (1014), a non-delayed signal-capture element (1016), a delayed signal-capture element (1018) and a comparator (1024). The non-delayed signal-capture element (1016) captures an output from the processing logic (1014) at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element (1018) also captures a value from the processing logic (1014). An error detection circuit (1026) and error correction circuit (1028) detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator (1024). The comparator (1024) compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

公开(公告)号：EP0766092B1

公开(公告)日：2004-12-01

申请号：EP96115167.7

申请日：1996-09-20

申请人： Infineon Technologies AG

发明人： Dallmann, Achim, Dipl.-Phys. ,  Bode, Hans-Jörgen, Dipl.-Ing.

IPC分类号： G01R31/3185 ,  G11C29/00 ,  G06F11/16

CPC分类号： G11C29/38 ,  G01R31/318566 ,  G06F11/1608

摘要： The circuit is designed for easy testing by supplying an input test pattern to a common input terminal (5), selectively coupled to the input of each of the identical circuit blocks (1,2). An evaluation stage (10) compares the output test patterns received from each of the identical circuit blocks, to provide an external fault signal when the compared output test patterns differ from one another. Pref. the circuit is supplied with an external clock signal, used for triggering a sampling control signal with a shorter pulse duration used by a sampling stage (14) supplying the fault signal provided by the evaluation stage to a circuit output terminal (7).

公开(公告)号：EP1168178A3

公开(公告)日：2002-04-03

申请号：EP01120968.1

申请日：1994-10-12

申请人： Hitachi, Ltd.

发明人： Kanekawa, Nobuyasu ,  Suzuki, Shoji ,  Sato, Yoshimichi ,  Tashiro, Korefumi ,  Bekki, Keisuke ,  Sato, Hiroshi ,  Nohmi, Makoto ,  Ohtsuji, Shinya

IPC分类号： G06F11/16 ,  G06F17/50

CPC分类号： G05B9/03 ,  G06F11/0763 ,  G06F11/0796 ,  G06F11/085 ,  G06F11/1608 ,  G06F11/1695 ,  G06F11/188 ,  G06F11/2215

摘要： The present invention relates to a self-checking circuit and a method of its configuration. More particularly, it concerns a self-checking circuit useful for highly reliable system configuration. As for a logic circuit having error detection function that has function blocks of feeding out a plurality of signals at least duplexed, compares the output signals of the function blocks, and detects an error on the basis of results of the comparison, it comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect the error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to the both output signals exist.

公开(公告)号：EP0410212A3

公开(公告)日：1994-06-01

申请号：EP90113285.2

申请日：1990-07-11

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Schwartz, Rolf, Dipl.-Ing.

IPC分类号： G06F1/12 ,  G06F11/18

CPC分类号： G06F11/1604 ,  G06F1/12 ,  G06F11/1608

摘要： Eine zweikanalige, federtolerante Taktgeberanordnung enthält zwei Taktgeber (TG1, TG2), die je einen Oszillator (Q1, Q2) enthalten. Die Frequenz des Oszillators des einen Taktgebers (TG1) ist niedriger als die des anderen, synchronisierten Takt­gebers (TG2). Dieser vergleicht die Phasendifferenz zwischen seinem Ausgangssignal und dem des anderen. Überschreitet die Phasendifferenz einen vorgegebenen Betrag, wird ein Impuls aus dem Ausgangssignal des Oszillators (Q2) ausgeblendet. Die Erfindung wird angewandt bei redundante Prozeßsteuer- und -leitsystemen.

公开(公告)号：EP0286879B1

公开(公告)日：1992-05-27

申请号：EP88104686.6

申请日：1988-03-23

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Kessler, Heinrich, Dipl.-Phys.

IPC分类号： G06F1/04 ,  G06F11/16 ,  H03L7/00

CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F1/08 ,  G06F11/1608 ,  G06F11/20 ,  H03L7/00