公开(公告)号：EP0907183A2

公开(公告)日：1999-04-07

申请号：EP98117000.4

申请日：1998-09-08

申请人： Hitachi, Ltd. ,  Hitachi ULSI Systems Co.,Ltd.

发明人： Sasaki, Toshio ,  Tanaka, Yuji ,  Yanagisawa, Kazumasa ,  Tanaka, Hitoshi ,  Sato, Jun ,  Miyamoto, Takashi ,  Ohtsuka, Mariko ,  Nakanishi, Satoru ,  Ayukawa, Kazushige ,  Watanabe, Takao

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器堆和为多个存储器堆提供的一个控制电路。 分别提供用于分别执行+1或-1算术运算的算术电路以对应于各个存储器堆并且以级联形式电连接。 初始级运算电路的输入端提供有地址设置固定地址信号。 提供给下一个和随后的运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器堆的信号）。 与上面提到的每个算术电路相关地提供的比较器对存储器访问时输入的地址信号和地址信号之间的一致性进行比较。 根据得到的一致信号选择相应的存储器块。

公开(公告)号：EP0907183B1

公开(公告)日：2004-12-22

申请号：EP98117000.4

申请日：1998-09-08

申请人： Hitachi, Ltd. ,  Hitachi ULSI Systems Co.,Ltd.

发明人： Sasaki, Toshio ,  Tanaka, Yuji ,  Yanagisawa, Kazumasa ,  Tanaka, Hitoshi ,  Sato, Jun ,  Miyamoto, Takashi ,  Ohtsuka, Mariko ,  Nakanishi, Satoru ,  Ayukawa, Kazushige ,  Watanabe, Takao

IPC分类号： G11C8/00

CPC分类号： G11C8/12

公开(公告)号：EP0907183A3

公开(公告)日：1999-09-29

申请号：EP98117000.4

申请日：1998-09-08

申请人： Hitachi, Ltd. ,  Hitachi ULSI Systems Co.,Ltd.

发明人： Sasaki, Toshio ,  Tanaka, Yuji ,  Yanagisawa, Kazumasa ,  Tanaka, Hitoshi ,  Sato, Jun ,  Miyamoto, Takashi ,  Ohtsuka, Mariko ,  Nakanishi, Satoru ,  Ayukawa, Kazushige ,  Watanabe, Takao

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.