公开(公告)号：EP0131277A3

公开(公告)日：1986-06-11

申请号：EP84107914

申请日：1984-07-06

Applicant: Honeywell Information Systems Inc.

Inventor： Hooker, Lane K. ,  Howell, Thomas H. ,  Ferrell, Charles W.

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/084

Abstract: A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.

Abstract translation: 多处理器计算机系统具有存储到高速缓存布置，其中系统的每个处理器单元具有其自己的唯一高速缓冲存储器单元。 由任何一个处理器单元操作的数据被存储在与该处理器单元相关联的高速缓冲存储器中。 当另一个处理器单元需要如此修改的数据块时，将所请求的数据直接传送到请求处理器单元，而不必首先将数据传送到共享的主存储器。 还规定了在规定的条件下将数据从缓存传送到主存储器，但不作为转移到请求处理器的前提条件。