公开(公告)号：EP0049159A2

公开(公告)日：1982-04-07

申请号：EP81304502.8

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Yu, Kin C. ,  Goss, Gary J.

IPC分类号： G06F3/04

CPC分类号： G06F13/4226 ,  G06F13/124 ,  G06F13/4022

摘要： A data processing system includes a CPU2, a main memory (4) subsystem, and a communication subsystem (8) all coupled to a system bus (16). Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge (immediate response), a negative acknowledge (the unit is busy), and a quasi-negative response (the unit will probably be ready soon). To expedite the response in the case of the transfer over the system bus of an input/output order from the central processing subsystem to the communication subsystem, the bus interface 30 in the communication system stores a positive acknowledge or a negative acknowledge signal for each communication channel. The signal is set to indicate a negative acknowledge when the previous input/ output order filled the last communication control block. The signal is set to indicate a positive acknowledge when the previous input/output order emptied the communication control block.

公开(公告)号：EP0049157A3

公开(公告)日：1984-04-25

申请号：EP81304500

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Kachemov, Angelo David ,  Yu, Kin C. ,  Hirtle, Allen C. ,  Goss, Gary J.

IPC分类号： G06F03/04

CPC分类号： G06F13/225

摘要： Polling means for polling a plurality of devices with receive and transmit channel numbers. The channel numbers are held in a register 504 and a recirculatory FIFO memory 500, and circulated through the register and memory, the channel number in register 504 polling the devices via line adapter 66. The channel number sequence defines the priorities of the channels, receive channels first then transmit channels. On a device response, the channel number is held in register 504 while the other channel numbers recirculate, so that on the next polling, a responding receive channel has top priority while a responding transmit channel has bottom priority. A counter 514 determines the mode of operation (initialize, scan, etc.) and a flip-flop 524 provides the receive/transmit bit of each channel number.

摘要翻译： 轮询用于轮询具有接收和发送信道号的多个设备。 信道号保存在寄存器504和再循环FIFO存储器500中，并通过寄存器和存储器循环，寄存器504中的通道号通过线路适配器66轮询设备。信道号序列定义了信道的优先级，接收 信道首先传输信道。 在设备响应上，通道号保持在寄存器504中，而其他通道号再循环，使得在下一次轮询时，响应的接收通道具有最高优先级，而响应的发送信道具有最低优先级。 计数器514确定操作模式（初始化，扫描等），并且触发器524提供每个通道号的接收/发送位。

公开(公告)号：EP0049160A3

公开(公告)日：1984-05-30

申请号：EP81304503

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Yu, Kin C. ,  Goss, Gary J.

IPC分类号： G06F03/04

CPC分类号： G06F9/4825 ,  G06F13/124 ,  G06F13/423 ,  G06F15/167

摘要： A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer 32, a line microprocessor 56 for communicating with the communication lines 17 and a shared memory 44, and an 1/0 microprocessor 36 for communicating with the shared memory 44 and the central processing unit and main memory (via 16). The line microprocessor 56, desiring the communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory 44 with a binary number indicative of the predetermined time delay. The 1/0 microprocessor 56 adds the output of the free running timer 32 to the binary number, stores the result in a location in a random access memory 40, and periodically compares the result against the free running timer output. The 1/0 microprocessor loads a second mailbox (in 44) with a control character when the results of the comarison indicate that the predetermined time delay is accomplished. The line microprocessor responds to the information in the second mailbox to communicate with the specified communication line.

摘要翻译： 数据处理系统包括中央处理单元，主存储器和服务多个通信线路的通信子系统。 通信子系统包括自由运行定时器32，用于与通信线路17和共享存储器44进行通信的线路微处理器56以及用于与共享存储器44以及中央处理单元和主存储器进行通信的I / O微处理器36 通过16）。 在预定时间延迟之后希望与指定通信线路通信的线路微处理器56以指示预定时间延迟的二进制数加载共享存储器44中的第一邮箱。 I / O微处理器56将自由运行定时器32的输出添加到二进制数，将结果存储在随机存取存储器40中的位置，并且周期性地将结果与自由运行定时器输出进行比较。 当比较结果表明预定的时间延迟完成时，I / O微处理器加载具有控制字符的第二个邮箱（在44中）。 线路微处理器响应第二个邮箱中的信息与指定的通信线路进行通信。

公开(公告)号：EP0049157A2

公开(公告)日：1982-04-07

申请号：EP81304500.2

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Hirtle, Allen C. ,  Goss, Gary J. ,  Kachemov, Angelo David ,  Yu, Kin C.

IPC分类号： G06F3/04

CPC分类号： G06F13/225

摘要： Polling means for polling a plurality of devices with receive and transmit channel numbers. The channel numbers are held in a register 504 and a recirculatory FIFO memory 500, and circulated through the register and memory, the channel number in register 504 polling the devices via line adapter 66. The channel number sequence defines the priorities of the channels, receive channels first then transmit channels. On a device response, the channel number is held in register 504 while the other channel numbers recirculate, so that on the next polling, a responding receive channel has top priority while a responding transmit channel has bottom priority. A counter 514 determines the mode of operation (initialize, scan, etc.) and a flip-flop 524 provides the receive/transmit bit of each channel number.

摘要翻译： 轮询用于轮询具有接收和发送信道号的多个设备。 信道号保存在寄存器504和再循环FIFO存储器500中，并通过寄存器和存储器循环，寄存器504中的通道号通过线路适配器66轮询设备。信道号序列定义了信道的优先级，接收 信道首先传输信道。 在设备响应上，通道号保持在寄存器504中，而其他通道号再循环，使得在下一次轮询时，响应的接收通道具有最高优先级，而响应的发送信道具有最低优先级。 计数器514确定操作模式（初始化，扫描等），并且触发器524提供每个通道号的接收/发送位。

公开(公告)号：EP0049159A3

公开(公告)日：1984-05-16

申请号：EP81304502

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Yu, Kin C. ,  Goss, Gary J.

IPC分类号： G06F03/04

CPC分类号： G06F13/4226 ,  G06F13/124 ,  G06F13/4022

摘要： A data processing system includes a CPU2, a main memory (4) subsystem, and a communication subsystem (8) all coupled to a system bus (16). Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge (immediate response), a negative acknowledge (the unit is busy), and a quasi-negative response (the unit will probably be ready soon). To expedite the response in the case of the transfer over the system bus of an input/output order from the central processing subsystem to the communication subsystem, the bus interface 30 in the communication system stores a positive acknowledge or a negative acknowledge signal for each communication channel. The signal is set to indicate a negative acknowledge when the previous input/ output order filled the last communication control block. The signal is set to indicate a positive acknowledge when the previous input/output order emptied the communication control block.

公开(公告)号：EP0049158A3

公开(公告)日：1984-05-02

申请号：EP81304501

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Yu, Kin C. ,  Goss, Gary J.

IPC分类号： G06F03/04

CPC分类号： G06F13/24 ,  G06F13/385 ,  G06F15/167

摘要： A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The 1/0 microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory 44. The line microprocessor is controlled by a PROM 58 and channel control programms (CCP's) in a RAM 60, and uses a work RAM 52 for data storage; the 1/0 microprocessor is controlled by a PROM 38 and uses a work RAM 40 for data storage. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

公开(公告)号：EP0049160A2

公开(公告)日：1982-04-07

申请号：EP81304503.6

申请日：1981-09-29

申请人： Honeywell Information Systems Inc.

发明人： Yu, Kin C. ,  Goss, Gary J.

IPC分类号： G06F3/04

CPC分类号： G06F9/4825 ,  G06F13/124 ,  G06F13/423 ,  G06F15/167

摘要： A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer 32, a line microprocessor 56 for communicating with the communication lines 17 and a shared memory 44, and an 1/0 microprocessor 36 for communicating with the shared memory 44 and the central processing unit and main memory (via 16). The line microprocessor 56, desiring the communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory 44 with a binary number indicative of the predetermined time delay. The 1/0 microprocessor 56 adds the output of the free running timer 32 to the binary number, stores the result in a location in a random access memory 40, and periodically compares the result against the free running timer output. The 1/0 microprocessor loads a second mailbox (in 44) with a control character when the results of the comarison indicate that the predetermined time delay is accomplished. The line microprocessor responds to the information in the second mailbox to communicate with the specified communication line.

摘要翻译： 数据处理系统包括中央处理单元，主存储器和服务多个通信线路的通信子系统。 通信子系统包括自由运行定时器32，用于与通信线路17和共享存储器44进行通信的线路微处理器56以及用于与共享存储器44以及中央处理单元和主存储器进行通信的I / O微处理器36 通过16）。 在预定时间延迟之后希望与指定通信线路通信的线路微处理器56以指示预定时间延迟的二进制数加载共享存储器44中的第一邮箱。 I / O微处理器56将自由运行定时器32的输出添加到二进制数，将结果存储在随机存取存储器40中的位置，并且周期性地将结果与自由运行定时器输出进行比较。 当比较结果表明预定的时间延迟完成时，I / O微处理器加载具有控制字符的第二个邮箱（在44中）。 线路微处理器响应第二个邮箱中的信息与指定的通信线路进行通信。