ACCESS METHOD AND DEVICE FOR MESSAGE-TYPE MEMORY MODULE
    2.
    发明授权
    ACCESS METHOD AND DEVICE FOR MESSAGE-TYPE MEMORY MODULE 有权
    用于消息类型存储器模块的访问方法和装置

    公开(公告)号:EP3015986B1

    公开(公告)日:2017-10-04

    申请号:EP14832194.6

    申请日:2014-07-31

    IPC分类号: G06F11/08 G06F11/10

    摘要: The present invention discloses a memory access apparatus for a message-type memory module, where the apparatus includes: a read-write module, configured to store, to a corresponding DRAM, an SCBC to be stored within a current read-write cycle; and a processing module, configured to: calculate one group of error detecting code for each SCBC in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row; where the read-write module is further configured to: store the error detecting code in an (M+2) th DRAM in the memory row, and store the error correcting code in a Z th DRAM in the memory row, where Z is a positive integer, 1 ‰¤ Z ‰¤ (M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. Embodiments of the present invention further provide a corresponding method. According to the technical solutions of the present invention, fine-granularity encoding protection is performed in a basic read-write unit of SCBC, and variable-granularity memory access is supported, so that error-correcting can be implemented for any multi-bit error in a single DRAM.

    摘要翻译: 本发明公开了一种消息类型内存模块的内存访问装置,所述装置包括:读写模块,用于将待存储在当前读写周期内的SCBC存储到对应的DRAM中; 处理模块,用于为存储器行中每个SCBC计算一组错误检测码,并为存储器行中的所有SCBC计算一组纠错码; 其中,所述读写模块还用于:将所述错误检测码存储在所述存储器行的第(M + 2)DRAM中,并将所述错误校正码存储在所述存储器行中的第Z DRAM中,其中Z为 (M + 1),连续(M + 1)存储行中的纠错码被存储在不同的DRAM中。 本发明的实施例还提供了相应的方法。 根据本发明的技术方案,在SCBC的基本读写单元中执行细粒度编码保护,并且支持可变粒度存储器访问,从而可以对任何多比特错误执行纠错 在单个DRAM中。

    METHOD, DEVICE AND SYSTEM FOR MEMORY ACCESS
    3.
    发明公开
    METHOD, DEVICE AND SYSTEM FOR MEMORY ACCESS 审中-公开
    SPEICHERZUGANGSVERFAHREN,-VORRICHTUNG UND -SYSTEM

    公开(公告)号:EP3021222A1

    公开(公告)日:2016-05-18

    申请号:EP14835213.1

    申请日:2014-08-07

    IPC分类号: G06F11/00

    CPC分类号: G06F11/008 G06F11/1004

    摘要: Embodiments of the present invention provide a memory access method, device, and system, so as to provide a hierarchical and flexible method for setting a memory reliability level to implement a memory access mechanism for different running object types and different reliability levels. The method provided in the embodiment of the present invention includes: receiving, by a memory device, reliability level information of a running object of a processor sent by the processor; establishing a first mapping relationship and a second mapping relationship according to the reliability level information of the running object; receiving an access request sent by the processor; and accessing data of the running object according to the access request and the first mapping relationship, and accessing error-tolerant code of the running object according to the access request and the second mapping relationship.

    摘要翻译: 本发明的实施例提供了一种存储器访问方法,设备和系统,以便提供一种用于设置存储器可靠性级别以实现用于不同运行对象类型和不同可靠性级别的存储器访问机制的分层和灵活的方法。 本发明实施例提供的方法包括:由存储装置接收由处理器发送的处理器的运行对象的可靠性级别信息; 根据运行对象的可靠性等级信息建立第一映射关系和第二映射关系; 接收处理器发送的访问请求; 以及根据所述访问请求和所述第一映射关系访问所述运行对象的数据,以及根据所述访问请求和所述第二映射关系访问所述运行对象的容错代码。

    PHOTOGRAPHING CONTROL METHOD AND TERMINAL
    4.
    发明公开

    公开(公告)号:EP3790271A1

    公开(公告)日:2021-03-10

    申请号:EP18924567.3

    申请日:2018-06-30

    摘要: Embodiments of this application disclose a shooting control method and a terminal and relate to the field of terminal technologies. Even if a user forgets to tap a recording start button on a video recording viewfinder screen, the terminal can still record a video, thereby improving human-machine interaction performance of the terminal. A specific solution includes: displaying, by a terminal, a first screen that is not a video recording viewfinder screen; receiving, by the terminal, a first operation of a user on the first screen; in response to the first operation, displaying a video recording viewfinder screen (namely, a second screen), starting to record a first video, and buffering the recorded first video; if the terminal detects a second operation, in response to the detected second operation, stopping, by the terminal, video recording, and displaying a third screen used to prompt the user to determine whether to save the first video; and saving or deleting the first video according to a selection operation of the user on the third screen. The second screen includes a recording start button, and the recording start button is used to trigger the terminal to start video recording.

    ELECTRONIC SYSTEM, CAMERA MODULE, AND SYSTEM ON CHIP

    公开(公告)号:EP4184423A1

    公开(公告)日:2023-05-24

    申请号:EP20947495.6

    申请日:2020-07-30

    IPC分类号: G06T3/40

    摘要: An electronic system (200), a camera module (190, or 210), a SoC (110, or 220), and an electronic device (100) are disclosed. The camera module (210) includes a first bidirectional interface (2101). The SoC (220) includes a second bidirectional interface (2201). The second bidirectional interface (2201) is coupled to the first bidirectional interface (2101), and the first bidirectional interface (2101) and the second bidirectional interface (2201) support a same bidirectional data communication interface protocol. The camera module (190, or 210) can obtain image data, and perform first image processing on the image data to obtain a first image processing result. The SoC (110, or 220) can perform second image processing on the first image processing result to obtain a second image processing result. In this way, the camera module (210) and the SoC (220) are connected to each other through the bidirectional interfaces (2101, and 2201) that support the bidirectional data communication interface protocol, to improve flexibility of an interface between the camera module (190, or 210) and the SoC (110, or 220), so that the camera module (190, or 210) flexibly processes the image data.

    ACCESS METHOD AND DEVICE FOR MESSAGE-TYPE MEMORY MODULE
    6.
    发明公开
    ACCESS METHOD AND DEVICE FOR MESSAGE-TYPE MEMORY MODULE 有权
    用于消息类型存储器模块的访问方法和装置

    公开(公告)号:EP3015986A1

    公开(公告)日:2016-05-04

    申请号:EP14832194.6

    申请日:2014-07-31

    IPC分类号: G06F11/08

    摘要: The present invention discloses a memory access apparatus for a message-type memory module, where the apparatus includes: a read-write module, configured to store, to a corresponding DRAM, an SCBC to be stored within a current read-write cycle; and a processing module, configured to: calculate one group of error detecting code for each SCBC in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row; where the read-write module is further configured to: store the error detecting code in an (M+2) th DRAM in the memory row, and store the error correcting code in a Z th DRAM in the memory row, where Z is a positive integer, 1 ≤ Z ≤ (M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. Embodiments of the present invention further provide a corresponding method. According to the technical solutions of the present invention, fine-granularity encoding protection is performed in a basic read-write unit of SCBC, and variable-granularity memory access is supported, so that error-correcting can be implemented for any multi-bit error in a single DRAM.

    摘要翻译: 本发明公开了一种消息类型内存模块的内存访问装置,所述装置包括:读写模块,用于将待存储在当前读写周期内的SCBC存储到对应的DRAM中; 处理模块,用于为存储器行中每个SCBC计算一组错误检测码,并为存储器行中的所有SCBC计算一组纠错码; 其中,所述读写模块还用于:将所述错误检测码存储在所述存储器行的第(M + 2)DRAM中,并将所述错误校正码存储在所述存储器行中的第ZDRAM中,其中Z为正数 整数,1≤Z≤(M + 1),连续(M + 1)存储行中的纠错码存储在不同的DRAM中。 本发明的实施例还提供了相应的方法。 根据本发明的技术方案,在SCBC的基本读写单元中执行细粒度编码保护,并且支持可变粒度存储器访问,从而可以对任何多比特错误执行纠错 在单个DRAM中。

    APPARATUS AND METHOD FOR EXECUTING ATOMIC OPERATIONS

    公开(公告)号:EP4318237A1

    公开(公告)日:2024-02-07

    申请号:EP21938472.4

    申请日:2021-04-30

    IPC分类号: G06F9/54

    摘要: An apparatus and a method for performing an atomic operation are provided. The apparatus for performing an atomic operation includes a remote direct memory access network interface card RNIC and an input output memory management unit IOMMU. The RNIC is configured to send a memory reading instruction to the IOMMU, where the memory reading instruction includes a target storage address. The IOMMU is configured to: read, in an exclusive manner, arithmetical data from target storage space corresponding to the target storage address, and send the arithmetical data to the RNIC, where the target storage space is provided by a memory. The RNIC is further configured to: perform an arithmetical operation on the arithmetical data to obtain an arithmetical result, and write the arithmetical result into the target storage space by using the IOMMU. The apparatus basically ensures consistency of data storage in the memory, and avoids a data inconsistency problem.

    DATA PROCESSING APPARATUS AND METHOD
    8.
    发明公开

    公开(公告)号:EP4206932A1

    公开(公告)日:2023-07-05

    申请号:EP20954498.0

    申请日:2020-09-24

    IPC分类号: G06F11/30

    摘要: A data processing apparatus (100) and a method are disclosed. The data processing apparatus (100) includes a remote direct memory access RDMA module (110), a home agent HA module (120), and a memory module (130). The HA module (120) performs calculation on local data and an operand in an RDMA packet, and writes an obtained calculation result into the memory module (130) through a non-bus interface, which can help prevent reading of the local data from the memory module (130) through a bus and writing of the calculation result into the memory module (130) through the bus. Therefore, the data processing apparatus (100) can optimize a calculation part in a node that performs collective communication, which helps reduce an inter-node communication delay. In addition, the data processing apparatus (100) can reduce a quantity of bus access times, thereby helping reduce bandwidth consumption of the bus.

    ENERGY-EFFICIENT DISPLAY PROCESSING METHOD, AND APPARATUS

    公开(公告)号:EP4053783A1

    公开(公告)日:2022-09-07

    申请号:EP20891976.1

    申请日:2020-11-17

    IPC分类号: G06T1/20 G06T15/00

    摘要: Embodiments of this application provide an energy-efficient display processing method and a device, and relate to the field of electronic technologies, so that graphics processing subsystems with different performance and power consumption can be switched to based on complexity of different to-be-displayed GUIs, to perform GUI display processing. This can reduce overall power consumption of an electronic device and improve energy efficiency of the electronic device. A specific solution is as follows: The electronic device includes a first graphics processing subsystem, a second graphics processing subsystem, and a screen. The first graphics processing subsystem includes a first application processor, a first graphics processing unit, and a first memory. The second graphics processing subsystem includes a second application processor, a second graphics processing unit, and a second memory. The first graphics processing unit renders a first GUI. The screen displays the first GUI. The second graphics processing unit renders a second GUI, and the second GUI and the first GUI belong to different interface types. The screen displays the second GUI. Embodiments of this application are used for display processing.

    DATA PROCESSING METHOD AND APPARATUS
    10.
    发明公开

    公开(公告)号:EP3736765A1

    公开(公告)日:2020-11-11

    申请号:EP19741008.7

    申请日:2019-01-15

    IPC分类号: G06T1/20

    摘要: A data processing method and apparatus are disclosed. The method includes: obtaining R groups of proposal region sequences (201), where each group of proposal region sequence includes a plurality of proposal regions; invoking a VRPAC instruction to calculate an area of each proposal region in each group of proposal region sequence (202); for a j th group of proposal region sequence in the R groups of proposal region sequences, invoking a VIOU instruction and a VAADD instruction to determine j suppression matrices of the j th group of proposal region sequence and determine a suppression vector of the j th group of proposal region sequence based on the j suppression matrices (203); and determining an unsuppressed proposal region based on a suppression vector of each group of proposal region sequence (204). The method reduces invoked instructions, reduces instruction execution steps, and shortens a time used in NMS calculation.