公开(公告)号：EP4428696A1

公开(公告)日：2024-09-11

申请号：EP22897463.0

申请日：2022-10-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： WAN, Bo ,  JIANG, Yifei ,  FAN, Henglong

IPC: G06F12/0888

CPC classification number: Y02D10/00 ,  G06F12/1009 ,  G06F12/0888 ,  G06F12/1027

Abstract: Embodiments of this application disclose a translation lookaside buffer maintenance method and a related device. The method is applied to an electronic device, the electronic device includes a plurality of physical central processing units CPUs, a first process is run on the electronic device, the first process currently includes M first threads, the M first threads are currently being respectively run on M physical CPUs of the plurality of physical CPUs, and M is an integer greater than or equal to 1. The method includes: determining a physical CPU range S1 currently corresponding to the first process, where the physical CPU range S1 includes the M physical CPUs on which the first threads in the first process are currently being run; and updating, based on page table information maintained by the first process, translation lookaside buffer TLB information maintained by all physical CPUs in the physical CPU range S 1. According to embodiments of this application, a TLB maintenance delay can be reduced.

公开(公告)号：EP4152149A1

公开(公告)日：2023-03-22

申请号：EP21822232.1

申请日：2021-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： JIANG, Yifei ,  ZHAO, Siqi ,  WAN, Bo

IPC: G06F9/455

Abstract: A method for handling an exception or interrupt in a heterogeneous instruction set architecture is provided. A physical host to which the method is applied can support two instruction set architectures. When a secondary architecture virtual machine (302) triggers an exception or interrupt, a virtual machine monitor (303) may translate code of the exception or interrupt in a secondary instruction set architecture into code of the exception or interrupt in a primary instruction set architecture. The virtual machine monitor (303) may identify the code of the exception or interrupt in the primary instruction set architecture. The virtual machine monitor (303) identifies, based on the translated code, a type of the exception or interrupt triggered by the secondary architecture virtual machine (302), to handle the exception or interrupt. In this way, the virtual machine monitor (303) may identify and handle the exception or interrupt triggered by the secondary architecture virtual machine (302). This can ensure system stability, enable a heterogeneous instruction set virtual machine to run properly, and build a diversified software ecosystem.

公开(公告)号：EP4195020A1

公开(公告)日：2023-06-14

申请号：EP21857282.4

申请日：2021-06-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： JIANG, Yifei ,  WAN, Bo ,  ZHAO, Siqi ,  LI, Mingwang

IPC: G06F3/06

Abstract: A computer device is disclosed. In a virtualization I/O procedure, a redirection apparatus in a processor is used to implement privilege level switching in a synchronization processing procedure, to directly switch from a virtualization privilege level of a VM to a user mode of a host, and perform corresponding exception processing. In an asynchronous processing procedure, an interrupt request may be asynchronously transferred by using a virtual event notification apparatus and an interrupt controller in the processor without passing through a kernel mode of the host. In both of a synchronous processing procedure and the asynchronous processing procedure of the device, overheads generated during switching are reduced, and performance of the computer device is improved.