公开(公告)号：EP4407471A9

公开(公告)日：2024-10-02

申请号：EP24153943.6

申请日：2024-01-25

Applicant: VMware LLC

Inventor： Nowatzyk, Andreas Georg ,  Subrahmanyam, Pratap ,  Akkawi, Isam Wadih ,  Nayak, Adarsh Seethanadi ,  Dua, Nishchay

IPC: G06F12/0811 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0888 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0811 ,  G06F2212/101620130101 ,  G06F2212/20520130101 ,  G06F2212/60120130101

Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.

公开(公告)号：EP4432106A1

公开(公告)日：2024-09-18

申请号：EP24160253.1

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KACHARE, Ramdas P. ,  LAU, Jimmy ,  BEYGI, Amir ,  SOLTANIYEH, Mohammadreza ,  LAC, Tinh ,  SUBBANNA, Divya ,  AGHAEE, Mostafa ,  ZHAO, Dongwan ,  TIEN, William ,  SINAI KAKODKAR, Varadraj Ninad ,  CARGNINI, Luis Vitorio

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/40 ,  G06F12/0868 ,  G06F12/0888 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F13/404 ,  G06F13/387 ,  G06F12/0868 ,  G06F13/1642 ,  G06F3/0656 ,  G06F3/0655 ,  G06F13/4027 ,  G06F12/0888 ,  G06F3/0658 ,  G06F3/0679

Abstract: A device (120) is disclosed. An interface (305) may connect the device (120) to a processor (110). The interface (305) may support a first protocol. The device (120) may include a first storage (315) for a data and a second storage (320) for the data. The second storage (320) may support a second protocol different from the first protocol. A controller (325) may be connected to the interface (305) and the first storage (315). A bridge (330) may be connected to the interface (305), the first storage (315), and the second storage (320). The bridge (330) may include a filter (335) configured to coordinate a data transfer between the first storage (315) and the second storage (320).

公开(公告)号：EP4430479A1

公开(公告)日：2024-09-18

申请号：EP22890871.1

申请日：2022-11-07

Applicant: Advanced Micro Devices, Inc.

Inventor： KELLEY, John ,  MOYER, Paul

IPC: G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F2212/50220130101 ,  G06F12/0888 ,  G06F12/126 ,  G06F12/128 ,  G06F12/0817 ,  G06F2212/101620130101

公开(公告)号：EP4428696A1

公开(公告)日：2024-09-11

申请号：EP22897463.0

申请日：2022-10-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： WAN, Bo ,  JIANG, Yifei ,  FAN, Henglong

IPC: G06F12/0888

CPC classification number: Y02D10/00 ,  G06F12/1009 ,  G06F12/0888 ,  G06F12/1027

Abstract: Embodiments of this application disclose a translation lookaside buffer maintenance method and a related device. The method is applied to an electronic device, the electronic device includes a plurality of physical central processing units CPUs, a first process is run on the electronic device, the first process currently includes M first threads, the M first threads are currently being respectively run on M physical CPUs of the plurality of physical CPUs, and M is an integer greater than or equal to 1. The method includes: determining a physical CPU range S1 currently corresponding to the first process, where the physical CPU range S1 includes the M physical CPUs on which the first threads in the first process are currently being run; and updating, based on page table information maintained by the first process, translation lookaside buffer TLB information maintained by all physical CPUs in the physical CPU range S 1. According to embodiments of this application, a TLB maintenance delay can be reduced.

公开(公告)号：EP3411791A1

公开(公告)日：2018-12-12

申请号：EP17703590.4

申请日：2017-01-25

Applicant: Microsoft Technology Licensing, LLC

Inventor： FOLTZ, Forrest Curtis

IPC: G06F9/50 ,  G06F12/0806

CPC classification number: G06F17/30132 ,  G06F3/0613 ,  G06F3/0643 ,  G06F3/067 ,  G06F9/5016 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0868 ,  G06F12/0877 ,  G06F12/0888 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/225 ,  G06F2212/261 ,  G06F2212/283 ,  G06F2212/502

Abstract: In various embodiments, methods and systems, for implementing modular data operations, are provided. A data access request, associated with data, is received at a data access component. The data access component selectively implements modular data operations functionality based on configuration settings. A translation table associated with a working set is accessed, based on the configuration settings of the data access component, to determine a location for executing the data access request. The data access request is executed using the cache store or a backing store associated with the working set. The data access request is executed using the location that is determined using the translation table of the working set. The data access request is executed using the cache store when the data is cached in the cache store and the data access requested is executed based on the backing store when the data is un-cached in the cache store.

公开(公告)号：EP2901288B1

公开(公告)日：2018-08-08

申请号：EP13776635.8

申请日：2013-09-26

Applicant: Qualcomm Incorporated

Inventor： DEBRUYNE, Leslie, Mark ,  DIEFFENDERFER, James, Norris ,  MCILVAINE, Michael, Scott ,  STEMPEL, Brian, Michael

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/10 ,  G06F12/0886 ,  G06F12/0888 ,  G06F9/30

CPC classification number: G06F12/0886 ,  G06F9/30149 ,  G06F9/3816 ,  G06F12/0888 ,  G06F12/10 ,  G06F2212/452

Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.

公开(公告)号：EP3323049A1

公开(公告)日：2018-05-23

申请号：EP16825102.3

申请日：2016-07-13

Applicant: Sios Technology Corporation

Inventor： RAZIN, Sergey A. ,  TO, Yokuki

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/264 ,  G06F2212/507

Abstract: A host device includes a controller configured to receive input/output (TO) access information associated with an IO workload, the IO access information identifying at least one of a read action and a write action associated with the IO workload over a period of time. Based upon the received IO access information associated with the storage element, the controller is configured to derive a predicted cache access ratio associated with the IO workload and relating a predicted number of cache accesses associated with the IO workload with at least one of a total number of read actions and a total number of write actions associated with the IO workload. When the predicted cache access ratio reaches a threshold cache access ratio value, the controller is configured to identify the IO workload as an IO workload candidate for caching by the host device.

公开(公告)号：EP2590082B1

公开(公告)日：2018-01-17

申请号：EP12190816.4

申请日：2012-10-31

Applicant: Renesas Electronics Corporation

Inventor： Kitahara, Takashi

IPC: G06F12/0875 ,  G06F12/0888 ,  G06F9/38

CPC classification number: G06F12/0888 ,  G06F9/3804 ,  G06F12/0875

Abstract: A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number.

公开(公告)号：EP3182293A1

公开(公告)日：2017-06-21

申请号：EP16198478.6

申请日：2016-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOONG, Seo

IPC: G06F12/0888 ,  H04L12/861

CPC classification number: G06F12/0895 ,  G06F12/0888 ,  G06F12/0891 ,  G06F2212/604

Abstract: Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.

Abstract translation: 提供了包括多个设备的处理器。 该处理器包括：源处理设备，被配置为识别来自另一设备的请求的数据;以及目的地处理设备，被配置为响应于使用基于信用的流量控制来自源处理设备的所识别的数据的请求，发送所识别的数据 使用基于信用的流量控制到源处理装置。 源处理装置包括用于基于信用的流量控制的信用缓冲器，信用缓冲器可分配以包括被配置为缓存由源处理装置接收的发送的识别数据的高速缓存区域。

公开(公告)号：EP3073386A1

公开(公告)日：2016-09-28

申请号：EP15275088.1

申请日：2015-03-27

Applicant: BRITISH TELECOMMUNICATIONS public limited company

Inventor： The designation of the inventor has not yet been filed

IPC: G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/122 ,  H04L67/2842

Abstract: Examples of the invention present an optimised method of managing a cache, where data items, such as video clips, are moved up in rank in a cache whenever it is requested, swapping rank with the data item above it. New data items not present in the cache are obtained and stored in the cache with a rank below the lowest ranked data item. If the cache is full, then the data item at the lowest rank is replaced by the newly requested data item. Thus data items that receive increasing numbers of requests are moved up the cache and thus have more protection from deletion.

Abstract translation: 本发明的示例呈现了一种管理高速缓存的优化方法，其中诸如视频剪辑的数据项在请求时在高速缓存中逐级向上移动，与其上的数据项交换秩。 高速缓存中不存在的新数据项被获取并存储在具有低于最低排名数据项的等级的高速缓存中。 如果缓存已满，则最低级别的数据项被新请求的数据项替换。 因此，接收越来越多请求的数据项向上移动缓存，因此具有更多的保护以免删除。