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公开(公告)号：EP4296714A1
公开(公告)日：2023-12-27
申请号：EP22810303.2
申请日：2022-04-28
发明人： DENG, Chaojun , WEI, Xiaoyun , YANG, Yong , ZANG, Dajun
摘要： An optical phased board, a manufacturing method, and an optical phased array system are disclosed, and pertain to the field of beam scanning technologies. The optical phased board includes a plurality of optical waveguide layers (1) and a plurality of isolation layers (2). Each optical waveguide layer (1) includes a plurality of optical waveguides (11), and the plurality of optical waveguides (11) are arranged side by side; and the plurality of optical waveguide layers (1) and the plurality of isolation layers (2) are arranged in a superimposed manner, and each isolation layer (2) is located between two adjacent optical waveguide layers (1). The optical phased board includes a two-dimensional optical waveguide array, and therefore can perform two-dimensional beam scanning. In addition, in comparison with performing two-dimensional beam scanning by using a two-dimensional optical antenna array, resolution and a scanning angle of the beam scanning can be improved.
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2.发明授权
公开(公告)号：EP3163779B1
公开(公告)日：2019-08-28
申请号：EP14898128.5
申请日：2014-07-22
发明人： LU, Yuchun , LI, Liang , ZHAI, Suping , ZANG, Dajun
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公开(公告)号：EP3442145A1
公开(公告)日：2019-02-13
申请号：EP16887607.6
申请日：2016-09-12
发明人： LU, Yuchun , LI, Liang , ZHAI, Suping , ZANG, Dajun
IPC分类号： H04L1/00
摘要： An encoding method, an encoder, and a decoder for dynamic power consumption control are provided. The encoder includes a control unit, an initial encoding unit, and L incremental encoding units. The control unit is configured to enable only the initial encoding unit in an RS (N 0 , K) operating mode to perform encoding or enable only the initial encoding unit and first j incremental encoding units in the L incremental encoding units in an RS (N j , K) operating mode to perform encoding. The initial encoding unit is configured to perform RS FEC encoding on m(x) to obtain a quotient D 0 (x) and a remainder R 0 (x) of x N 0 -K m(x) relative to g 0 (x). An (h+1) th incremental encoding unit is configured to obtain, according to a quotient D h (x) and a remainder R h (x), a quotient D h+1 (x) and a remainder R h+1 (x) of x N h+1 -K m(x) relative to g h+1 (x).
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公开(公告)号：EP3043497A1
公开(公告)日：2016-07-13
申请号：EP14842584.6
申请日：2014-08-11
发明人： LI, Zhijun , CHEN, Zhiqiang , ZANG, Dajun
IPC分类号： H04L1/00
CPC分类号： H04L25/14 , G06F17/00 , H04L1/0002 , H04L1/0026 , H04L12/00 , H04L12/6418 , H04L25/03866 , H04L25/03872
摘要： The present application discloses a data processing method and apparatus. The technical solutions of the present application include: coding received data; distributing the coded data to multiple PCS lanes; and performing self-synchronizing scramble separately for multiple data streams distributed to the multiple PCS lanes, where the multiple data streams are in a one-to-one correspondence with the multiple PCS lanes. The technical solutions provided by the present application may be used to reduce occupied logical resources during a data processing process at a physical layer.
摘要翻译： 本申请公开了一种数据处理方法和装置。 本申请的技术方案包括：对收到的数据进行编码; 将编码数据分配到多个PCS通道; 对分配给多个PCS通道的多个数据流分别进行自同步扰码，其中多个数据流与多个PCS通道一一对应。 本申请提供的技术方案可以用于减少物理层数据处理过程中占用的逻辑资源。
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5.发明公开
公开(公告)号：EP3863114A1
公开(公告)日：2021-08-11
申请号：EP19880245.6
申请日：2019-10-23
发明人： ZANG, Dajun , WANG, Cuicui , MO, Daochun , LU, Yuchun , WANG, Linchun
IPC分类号： H01P5/10
摘要： Embodiments of this application provide a balance-unbalance conversion apparatus, a communications device, and a communications system, and relate to the field of communications device technologies. The balance-unbalanced conversion apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The first balance signal connection section is configured to transmit a first component of a balance signal. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.
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公开(公告)号：EP3043497B1
公开(公告)日：2019-05-22
申请号：EP14842584.6
申请日：2014-08-11
发明人： LI, Zhijun , CHEN, Zhiqiang , ZANG, Dajun
IPC分类号： H04L1/00
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7.发明公开METHOD AND APPARATUS FOR DETERMINING FORWARD ERROR CORRECTION FRAME BOUNDARY AND DECODING SYSTEM 审中-公开用于确定前向纠错帧边界和解码系统的方法和设备
公开(公告)号：EP3163779A8
公开(公告)日：2017-07-12
申请号：EP14898128.5
申请日：2014-07-22
发明人： LU, Yuchun , LI, Liang , ZHAI, Suping , ZANG, Dajun
IPC分类号： H04L1/00
CPC分类号： H04L1/0083 , H03M13/1515 , H03M13/152 , H03M13/333 , H03M13/3746 , H04L1/00 , H04L7/048 , H05K999/99
摘要： The present invention provides a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system, which are mainly applicable to an RS code and a BCH code. The method includes: receiving data, where the data includes N+P consecutive symbols with a first symbol being a starting point, N consecutive symbols with the first symbol being a starting point that are in the N+P consecutive symbols constitute a first data block, and N consecutive symbols with a second symbol being a starting point that are in the N+P consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block; determining a first iterative item and a second iterative item of the second data block; determining, according to the s parameter values corresponding to the first data block and the first iterative item and the second iterative item of the second data block, s parameter values corresponding to the second data block; and determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame. The method for determining a frame boundary of an FEC frame disclosed in the present invention can improve efficiency of detecting a frame boundary of an FEC frame.
摘要翻译： 本发明提供了一种主要适用于RS码和BCH码的用于确定FEC帧的帧边界的方法和设备以及解码系统。 该方法包括：接收数据，该数据包括以第一个符号为起点的N + P个连续符号，其中第一个符号为N + P个连续符号中的起始点的N个连续符号构成第一数据块 并且具有在N + P个连续符号中的作为起始点的第二符号的N个连续符号构成第二数据块; 获取与所述第一数据块对应的s个参数值; 确定第二数据块的第一迭代项目和第二迭代项目; 根据所述第一数据块对应的s参数值以及所述第二数据块的第一迭代项和第二迭代项确定所述第二数据块对应的s个参数值; 根据所述第二数据块对应的s参数值确定所述第二符号是否为FEC帧的帧边界。 本发明公开的确定FEC帧的帧边界的方法可以提高检测FEC帧的帧边界的效率。
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8.发明公开
公开(公告)号：EP3618326A1
公开(公告)日：2020-03-04
申请号：EP19187975.8
申请日：2014-07-22
发明人： LU, Yuchun , LI, Liang , ZHAI, Suping , ZANG, Dajun
摘要： The present invention provides a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system, which are mainly applicable to an RS code and a BCH code. The method includes: receiving data, where the data includes N+P consecutive symbols with a first symbol being a starting point, N consecutive symbols with the first symbol being a starting point that are in the N+P consecutive symbols constitute a first data block, and N consecutive symbols with a second symbol being a starting point that are in the N+P consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block; determining a first iterative item and a second iterative item of the second data block; determining, according to the s parameter values corresponding to the first data block and the first iterative item and the second iterative item of the second data block, s parameter values corresponding to the second data block; and determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame. The method for determining a frame boundary of an FEC frame disclosed in the present invention can improve efficiency of detecting a frame boundary of an FEC frame.
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公开(公告)号：EP2442499B1
公开(公告)日：2014-07-09
申请号：EP10799396.6
申请日：2010-05-26
发明人： CHEN, Wumao , ZANG, Dajun
IPC分类号： H04L12/933
CPC分类号： H04L49/3045 , H04L49/101 , H04L49/254 , H04L49/3027 , H04L49/508
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10.发明公开DATA EXCHANGE METHOD AND DATA EXCHANGE STRUCTURE 有权DATENAUSTAUSCHVERFAHREN UND DATENAUSTAUSCHSTRUKTUR
公开(公告)号：EP2442499A1
公开(公告)日：2012-04-18
申请号：EP10799396.6
申请日：2010-05-26
发明人： CHEN, Wumao , ZANG, Dajun
IPC分类号： H04L12/56
CPC分类号： H04L49/3045 , H04L49/101 , H04L49/254 , H04L49/3027 , H04L49/508
摘要： A method for switching data is provided, which includes the following steps. An output port scheduler obtains state information of Virtual Output Queues (VOQs) and available state information of input port data channels and output port buffers. The output port scheduler sends scheduling request information to a Fabric Interface Controller (FIC) of an input port whose input port data channel is ready in input ports corresponding to non-empty VOQs pointing to an output port. After receiving the scheduling request information sent by the output port schedulers, the FIC of the selected input port selects to respond to a scheduling request of one output port scheduler, and sends the VOQ pointing to the output port in the selected input port to the output port buffer. The output port scheduler schedules the VOQ received by the output port buffer out of a switch chip. A structure for switching data is further provided. In this way, buffer resources of the switch chip are saved and the switching performance of the system is improved.
摘要翻译： 提供了一种切换数据的方法，包括以下步骤。 输出端口调度器获取虚拟输出队列（VOQ）的状态信息和输入端口数据通道和输出端口缓冲器的可用状态信息。 输出端口调度器向对应于指向输出端口的非空VOQ的输入端口准备好输入端口数据信道的输入端口的Fabric接口控制器（FIC）发送调度请求信息。 在接收到输出端口调度器发送的调度请求信息后，所选输入端口的FIC选择响应一个输出端口调度器的调度请求，并将指向所选输入端口的输出端口的VOQ发送到输出端 端口缓冲区。 输出端口调度器将由输出端口缓冲器接收的VOQ调度为交换芯片。 还提供了用于切换数据的结构。 以这种方式，节省了交换芯片的缓冲资源，提高了系统的交换性能。
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