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公开(公告)号：EP3813067A1
公开(公告)日：2021-04-28
申请号：EP19878916.6
申请日：2019-10-15
发明人： YU, Jingzhou , WANG, Linchun
摘要： This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row. The CAM may be applied to a network device such as a router.
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公开(公告)号：EP3151111B1
公开(公告)日：2018-10-17
申请号：EP14896520.5
申请日：2014-06-30
发明人： LI, Nan , WANG, Linchun , CHEN, Hongfei
IPC分类号： H04L12/741 , H04L12/947 , H04L12/933
摘要： A data processing method executed by a network apparatus, and a related device are provided. The data processing method executed by a network apparatus includes: receiving, by the i th processing circuit in a first circuit set, a first packet header and data D (1, i-1) , obtaining data D' (1, i) based on a first field in the first packet header, and sending the first packet header and data D (1, i) to the (i+1) th processing circuit in the first circuit set, where the data D (1, i) is obtained based on the data D (1, i-1) and the data D' (1, i) ; sending, by the i th processing circuit in the first circuit set, the data D (1, i) to the (i+1) th processing circuit in a second circuit set; and sending, by the i th processing circuit in the second circuit set, a second packet header to the (i+1) th processing circuit in the second circuit set. The solutions provided in embodiments of the present invention can help to increase a utilization rate of a processing resource and reduce packet processing complexity.
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3.发明公开INSTRUCTION SEQUENCE DETERMINATION METHOD AND ASSOCIATED DEVICE AND SYSTEM 审中-公开COMMAND结构测定方法及相关设备，系统
公开(公告)号：EP3147778A1
公开(公告)日：2017-03-29
申请号：EP14896488.5
申请日：2014-06-30
发明人： LI, Nan , WANG, Linchun
IPC分类号： G06F9/44
CPC分类号： G06F9/445 , G06F8/30 , G06F8/61 , G06F8/65 , G06F9/44 , H04L41/5054 , H04L41/5077 , H04L45/38 , H04L49/70
摘要： A method for determining instruction sequences, a related device, and a system. A method for determining instruction sequences may include: acquiring a function identifier; and determining M1 instruction sequences used to implement a function identified by the function identifier, where each instruction sequence in the M1 instruction sequences includes a unique entry instruction, and each instruction sequence in the M1 instruction sequences includes a unique exit instruction, where M1 is a positive integer, and the M1 instruction sequences are instruction sequences for creating a network packet processing program used to process a network packet. Solutions of embodiments of the present invention are advantageous for improving an extent of matching between a packet forwarding processing device and an instruction sequence that is executed by the packet forwarding processing device and used to process a network packet, and reducing an amount of invalid code run by the packet forwarding processing device.
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4.发明公开
公开(公告)号：EP3863114A1
公开(公告)日：2021-08-11
申请号：EP19880245.6
申请日：2019-10-23
发明人： ZANG, Dajun , WANG, Cuicui , MO, Daochun , LU, Yuchun , WANG, Linchun
IPC分类号： H01P5/10
摘要： Embodiments of this application provide a balance-unbalance conversion apparatus, a communications device, and a communications system, and relate to the field of communications device technologies. The balance-unbalanced conversion apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The first balance signal connection section is configured to transmit a first component of a balance signal. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.
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公开(公告)号：EP3799368A1
公开(公告)日：2021-03-31
申请号：EP20190054.5
申请日：2014-05-30
发明人： LI, Nan , WANG, Linchun
IPC分类号： H04L12/70 , H04L29/06 , H04L12/931 , H04L12/46 , H04L12/741 , H04L25/02
摘要： A packet edit processing method and a related device. The packet edit processing method includes: generating an input packet template based on N - to-be-edited protocol header fields of an input packet, and a preset protocol field mapping relationship, where the input packet template includes N protocol descriptors that are corresponding, in a one-to-one manner, to the N protocol header fields, arid the protocol field mapping relationship is a mapping relationship between a protocol field included in a protocol descriptor and a protocol field included in a protocol header field that has a correspondence with the protocol descriptor; performing edit processing on the input packet template to obtain an output packet template; and converting, based on the preset protocol field mapping relationship, M protocol descriptors included in the obtained output packet template into M protocol header fields of an output packet, and replacing the N protocol header fields in the input packet with the M protocol header fields to obtain the output packet. The foregoing solution helps reduce instruction complexity for packet edit processing and improve efficiency of packet edit processing.
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公开(公告)号：EP3139549A1
公开(公告)日：2017-03-08
申请号：EP14893121.5
申请日：2014-05-30
发明人： LI, Nan , WANG, Linchun
IPC分类号： H04L12/70
CPC分类号： H04L45/74 , H04L12/4633 , H04L12/4641 , H04L69/06 , H04L69/08 , H04L69/18
摘要： A packet edit processing method and a related device. The packet edit processing method includes: generating an input packet template based on N to-be-edited protocol header fields of an input packet, and a preset protocol field mapping relationship, where the input packet template includes N protocol descriptors that are corresponding, in a one-to-one manner, to the N protocol header fields, and the protocol field mapping relationship is a mapping relationship between a protocol field included in a protocol descriptor and a protocol field included in a protocol header field that has a correspondence with the protocol descriptor; performing edit processing on the input packet template to obtain an output packet template; and converting, based on the preset protocol field mapping relationship, M protocol descriptors included in the obtained output packet template into M protocol header fields of an output packet, and replacing the N protocol header fields in the input packet with the M protocol header fields to obtain the output packet. The foregoing solution helps reduce instruction complexity for packet edit processing and improve efficiency of packet edit processing.
摘要翻译： 分组编辑处理方法和相关设备。 分组编辑处理方法包括：基于输入分组的N个待编辑协议头字段和预设协议字段映射关系生成输入分组模板，其中输入分组模板包括N个对应的协议描述符， N协议报头字段是一对一的方式，协议字段映射关系是包括在协议描述符中的协议字段与协议报头字段中包含的协议字段之间的对应关系， 协议描述符 对所述输入分组模板执行编辑处理以获得输出分组模板; 并将所获得的输出分组模板中包含的M个协议描述符转换为输出分组的M个协议头部字段，并用M个协议头字段将输入分组中的N个协议头字段替换为 获取输出数据包。 上述解决方案有助于降低分组编辑处理的指令复杂度并提高分组编辑处理的效率。
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公开(公告)号：EP3706332A1
公开(公告)日：2020-09-09
申请号：EP18884804.8
申请日：2018-11-16
发明人： MO, Daochun , LIU, Qingzhi , XU, Xiaofei , LEI, Wenyang , WANG, Chuang , WANG, Linchun
IPC分类号： H04B10/40
摘要： This application discloses an optical backplane system, a switching system, and a switching system upgrade method. The optical backplane system includes a first upper-level optical interconnection module, a first lower-level optical interconnection module, and a second lower-level optical interconnection module. The first upper-level optical interconnection module includes M1 first interfaces and N1 second interfaces in connection relationships. The first lower-level optical interconnection module includes L1 third interfaces and K1 fourth interfaces in connection relationships. The second lower-level optical interconnection module includes L2 third interfaces and K2 fourth interfaces in connection relationships. The first upper-level optical interconnection module is connected to one of the L1 third interfaces of the first lower-level optical interconnection module by using one of the N1 second interfaces. The first upper-level optical interconnection module is connected to one of the L2 third interfaces of the second lower-level optical interconnection module by using another one of the N1 second interfaces. All the first interfaces and the fourth interfaces are configured to connect to processing modules. All M1, N1, K1, K2, L1, and L2 are greater than 1.
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公开(公告)号：EP3128437A1
公开(公告)日：2017-02-08
申请号：EP15785616.2
申请日：2015-04-02
发明人： LI, Nan , WANG, Linchun , CHEN, Hongfei
IPC分类号： G06F15/163 , G06F9/38
CPC分类号： G06F15/80 , G06F9/38 , G06F9/3826 , G06F9/3828 , G06F13/1605 , G06F13/4031 , G06F15/163 , G06F15/17 , G06F15/825 , G06F2207/3868
摘要： Disclosed are a data processing method, a processor, and a data processing device. The method comprises: an arbiter sends data D (a,1) to a first processing circuit; the first processing circuit processes the data D (a,1) to obtain data D (1,2) , the first processing circuit being a processing circuit among m processing circuits; the first processing circuit sends the data D (1,2) to a second processing circuit; the second processing circuit to an m th processing circuit separately process the received data; and the arbiter receives data D (m,a) sent by the m th processing circuit. The arbiter and the m processing circuits are components of the processor. The processor further comprises an (m+1) th processing circuit. Each processing circuit in the first processing circuit to the (m+1) th processing circuit can receive first data to be processed sent by the arbiter, and process the first data to be processed. The scheme is helpful to improve efficiency of data processing.
摘要翻译： 公开了一种数据处理方法，处理器和数据处理装置。 该方法包括：仲裁器将数据D（a，1）发送到第一处理电路; 第一处理电路处理数据D（a，1）以获得数据D（1,2），第一处理电路是m个处理电路中的处理电路; 第一处理电路将数据D（1,2）发送到第二处理电路; 第二处理电路到第m处理电路分别处理所接收的数据; 并且仲裁器接收由第m处理电路发送的数据D（m，a）。 仲裁器和m处理电路是处理器的组件。 处理器还包括第（m + 1）处理电路。 到第（m + 1）处理电路的第一处理电路中的每个处理电路可以接收由仲裁器发送的待处理的第一数据，并处理第一待处理数据。 该方案有助于提高数据处理的效率。
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公开(公告)号：EP3902215A1
公开(公告)日：2021-10-27
申请号：EP19908321.3
申请日：2019-12-31
发明人： HE, Zijian , LU, Hui , WANG, Linchun , YAN, Xingtao , LIU, Yang , YANG, Wenzong , YU, Jingzhou , YU, Xiang
IPC分类号： H04L12/803
摘要： This application provides a data transmission method and a network device. The method includes: sending, by a first network device, request information to a second network device; receiving, by the first network device, grant information sent by the second network device, where the grant information includes a first sequence number; determining, by the first network device, a first credit limit based on the first sequence number, where the first credit limit is an amount of data that is allowed to be sent by the first network device in a packet-distributed load sharing manner; and sending, by the first network device, data to the second network device based on the first credit limit. In the foregoing technical solution, the first network device determines, based on the grant information sent by the second network device, the amount of data that is allowed to be sent in the packet-distributed load sharing manner, and further sends data to the second network device based on the amount of data. This can avoid that an amount of data sent exceeds an amount of data that can be cached and ordered by the second network device, thereby avoiding out-of-order sending of data packets from the second network device.
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公开(公告)号：EP3506562A1
公开(公告)日：2019-07-03
申请号：EP17854892.1
申请日：2017-09-27
发明人： XU, Xiaofei , LIU, Qingzhi , ZHANG, Xiaojun , WANG, Linchun , YU, Jingzhou
IPC分类号： H04L12/00
摘要： A board registration method, a board, and a forwarding device are disclosed. The board includes a line card and a switch fabric card. The line card includes a fabric interface chip, and the fabric interface chip is optically interconnected to a switch fabric chip in at least one switch fabric card by using an optical fiber. An optical cross-connect device may further be added between the fabric interface chip and the switch fabric chip, and the optical cross-connect device, the fabric interface chip, and the switch fabric chip are all optically interconnected to each other by using an optical fiber. A line card registration method includes: obtaining, by the line card, line card information of the line card; and sending, by the line card, the line card information to the at least one switch fabric card through an optical interconnect path, so that the at least one switch fabric card registers the line card based on the line card information. The method can break through restrictions of a chassis or cabinet and a deployment position, thereby quickly completing deployment.
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