公开(公告)号：EP1595154A4

公开(公告)日：2006-05-10

申请号：EP03713598

申请日：2003-02-20

申请人： IBM

发明人： GATTIKER ANNE ,  GROSCH DAVID A ,  KNOX MARC D ,  MOTIKA FRANCO ,  NIGH PHIL ,  VAN HORN JODY ,  ZUCHOWSKI PAUL S

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.