公开(公告)号：EP1470583A4

公开(公告)日：2005-08-03

申请号：EP02789958

申请日：2002-11-26

Applicant: IBM

Inventor： POGGE BERNHARD H ,  YU ROY ,  PRASAD CHANDRIKA ,  NARAYAN CHANDRASEKHAR

IPC: H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate (1). A metallized feature (2) is formed in the top surface of a substrate, and a handling plate (35) is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via (20). The substrate may comprise a chip (44) having a device (30), e.g. a PE chip. The plate may be a wafer (65) attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices (30,60) fabricated therein, so that the process provides vertical wafer-level integration of the devices.

公开(公告)号：EP0806727A3

公开(公告)日：1998-05-20

申请号：EP97302760

申请日：1997-04-22

Applicant: IBM

Inventor： ALT PAUL MATTHEW ,  CHALCO PEDRO A ,  FURMAN BRUCE KENNETH ,  HORTON RAYMOND ROBERT ,  NARAYAN CHANDRASEKHAR ,  OWENS BENAL LEE JR ,  WARREN KEVIN WILSON ,  WRIGHT STEVEN LORENZ

IPC: G02F1/1343 ,  G02F1/13 ,  G02F1/1362 ,  G06F11/20 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G11C29/00

CPC classification number: G02F1/1309 ,  G02F2001/136272 ,  G09G3/3611 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2310/0297 ,  G09G2330/08 ,  G11C29/76 ,  Y10S345/904

Abstract: A matrix addressed display system designed so as to enable data line (22) repair by electronic mechanisms which is efficient and low in cost and thus increases yield. Such active data line (22) repair utilizes additional data driver (36) outputs, a defect map memory (48) in the TFT/LCD module and modification of the data stream to the data drivers (36) by additional circuits (42) between the display and the display adapter. A bus configuration on the display substrate is utilized which combines repair flexibility, low parasitic capacitance, and the ability to easily make the necessary interconnections. The number of interconnections is kept to a minimum, the connections are reliable, and the connections may be made with conventional wire bond or laser bond technology, or disk bond technology.