公开(公告)号：EP3408863A1

公开(公告)日：2018-12-05

申请号：EP17701352.1

申请日：2017-01-26

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： KHAZAKA, Rabih ,  THOLLIN, Benoît

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11505 ,  H01L2224/11822 ,  H01L2224/1184 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81208 ,  H01L2224/8184 ,  H01L2924/381 ,  H01L2924/00014

Abstract: The invention relates to an assembly comprising: - at least one first element (100) comprising at least one first electrically connecting contact pad (12); - at least one second element (200) comprising at least one second electrically connecting contact pad (21); and electrically and mechanically interconnecting means, characterised in that said electrically and mechanically interconnecting means comprise at least: - at least one first metal intermediate interconnecting element (13), on the surface of at least the first electrically connecting contact pad; - at least one sintered joint of metal microparticles or nanoparticles, which joint is stacked on top of the first metal intermediate interconnecting element; - the melting point of the first metal intermediate interconnecting element being above the sintering temperature of the metal microparticles or nanoparticles. The invention further relates to a process for manufacturing an assembly according to the invention.

公开(公告)号：EP3325208A1

公开(公告)日：2018-05-30

申请号：EP16747855.1

申请日：2016-07-19

Applicant: Northeastern University ,  University Of North Florida

Inventor： STAGON, Stephen, Peter ,  HUANG, Hanchen ,  ELLIOTT, Paul, Robert

IPC: B23K35/26 ,  B23K35/02 ,  H01L23/00

CPC classification number: B23K35/264 ,  B23K35/02 ,  B23K35/0227 ,  B23K35/0261 ,  B23K35/26 ,  B23K2101/40 ,  B23K2101/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05583 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/27418 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/2782 ,  H01L2224/29005 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29205 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/3201 ,  H01L2224/32012 ,  H01L2224/32501 ,  H01L2224/32506 ,  H01L2224/83099 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2924/01014 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/0102

Abstract: Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

公开(公告)号：EP2886243B1

公开(公告)日：2018-03-14

申请号：EP12879828.7

申请日：2012-06-30

Applicant: SENJU METAL INDUSTRY CO., LTD.

Inventor： YAMANAKA, Yoshie ,  TACHIBANA, Ken ,  YOSHIKAWA, Shunsaku ,  NOMURA, Hikaru

IPC: B23K35/26 ,  C22C13/00 ,  C22C13/02 ,  H01L21/60 ,  H05K3/34

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/0222 ,  B23K35/0261 ,  B23K35/26 ,  B23K35/262 ,  C22C13/00 ,  C22C13/02 ,  H01B1/02 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1301 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/2076 ,  H05K3/3457 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/00014

Abstract: A solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, which suppresses fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The present invention is a lead-free solder ball for electrodes of BGAs or CSPs consisting of 1.6 - 2.9 mass % of Ag, 0.7 - 0.8 mass % of Cu, 0.05 - 0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and excellent resistance to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment. At least one element selected from Fe, Co, and Pt in a total amount of 0.003 - 0.1 mass % or at least one element selected from Bi, In, Sb, P, and Ge in a total amount of 0.003 - 0.1 mass % may be added to this composition.

公开(公告)号：EP3154729A4

公开(公告)日：2018-02-28

申请号：EP15806611

申请日：2015-06-12

Applicant: ALPHA METALS

Inventor： GHOSHAL SHAMIK ,  KUMAR V SATHISH ,  VISHWANATH PAVAN ,  PANDHER RANJIT S ,  CHANDRAN REMYA ,  MUKHERJEE SUTAPA ,  SARKAR SIULI ,  SINGH BAWA ,  BHATKAL RAVINDRA MOHAN

IPC: B22F1/02 ,  B22F3/10 ,  B22F5/00 ,  B22F7/02 ,  B22F7/04 ,  B23K35/02 ,  B23K35/30 ,  C22C1/04 ,  H01L23/00 ,  H05K1/09

CPC classification number: B22F1/0044 ,  B22F1/02 ,  B22F3/1017 ,  B22F3/22 ,  B22F5/006 ,  B22F7/04 ,  B22F2007/047 ,  B22F2301/255 ,  B22F2999/00 ,  B23K1/0016 ,  B23K3/0607 ,  B23K35/0244 ,  B23K35/3006 ,  B23K2201/40 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L2221/68313 ,  H01L2221/68368 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05639 ,  H01L2224/11003 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/1144 ,  H01L2224/11505 ,  H01L2224/11848 ,  H01L2224/13139 ,  H01L2224/13294 ,  H01L2224/13295 ,  H01L2224/13311 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13363 ,  H01L2224/1338 ,  H01L2224/13384 ,  H01L2224/13387 ,  H01L2224/1339 ,  H01L2224/13393 ,  H01L2224/13411 ,  H01L2224/13439 ,  H01L2224/13444 ,  H01L2224/13455 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1349 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27003 ,  H01L2224/27009 ,  H01L2224/271 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27332 ,  H01L2224/27334 ,  H01L2224/27438 ,  H01L2224/2744 ,  H01L2224/27505 ,  H01L2224/2782 ,  H01L2224/27821 ,  H01L2224/27848 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/29311 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29363 ,  H01L2224/29364 ,  H01L2224/2938 ,  H01L2224/29384 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29455 ,  H01L2224/29464 ,  H01L2224/29469 ,  H01L2224/2949 ,  H01L2224/2969 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/75251 ,  H01L2224/75316 ,  H01L2224/7598 ,  H01L2224/81002 ,  H01L2224/81191 ,  H01L2224/8184 ,  H01L2224/81948 ,  H01L2224/83002 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/0463 ,  H01L2924/0503 ,  H01L2924/05032 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/2064 ,  H05K3/32 ,  H05K2203/1131 ,  B22F1/0018 ,  B22F1/025 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2924/01046 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01006 ,  H01L2924/01005 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

公开(公告)号：EP2960930A4

公开(公告)日：2017-07-12

申请号：EP14753874

申请日：2014-02-24

Applicant: FURUKAWA ELECTRIC CO LTD

Inventor： SATO SHUNICHIRO ,  KOJIMA NAOYUKI ,  HIKASA KAZUHITO ,  AMANO TOSHIAKI

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/743 ,  H01L24/75 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/2711 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27505 ,  H01L2224/292 ,  H01L2224/29294 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29364 ,  H01L2224/29366 ,  H01L2224/29369 ,  H01L2224/29381 ,  H01L2224/29384 ,  H01L2224/2939 ,  H01L2224/29495 ,  H01L2224/3201 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7532 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/27848

Abstract: An object of the present invention is to provide a connection structure that is able to suppress cracking and peeling in a joint surfaces between a pad part on a substrate (or a lead frame) and a porous metal layer and between a semiconductor element and the porous metal layer. A connection structure (I) for connecting a rear electrode of a semiconductor element to a substrate or a lead frame, wherein a porous metal layer (C) is provided so as to come into contact with at least the rear electrode of the semiconductor element, and the ratio [(B)/(A)] of a porosity of an intermediate portion in the thickness direction of an outer peripheral side part (B) of a region further towards the outside than the cross-section part formed at a position of a distance equivalent to the thickness of the porous metal layer (C) from the side surface toward the inside, to the porosity on the center side (A) after having excluded the outer peripheral side part (B), falls within the range of 1.10 to 1.60.

Abstract translation: 本发明的一个目的是提供一种连接结构，其能够抑制基板（或引线框架）上的焊盘部分与多孔金属层之间以及半导体元件与多孔层之间的接合表面中的裂缝和剥离 金属层。 一种连接结构（I），用于将半导体元件的背面电极连接到衬底或引线框架，其中提供多孔金属层（C）以至少与半导体元件的背面电极接触， 与比形成于该位置的截面部更靠外侧的区域的外周侧部分（B）的厚度方向的中间部分的空隙率[（B）/（A）]之比[（B）/ 与排除了外周侧部分（B）之后的中心侧（A）上的多孔金属层（C）的厚度相当的距离从侧面朝向内侧落入1.10的范围内 到1.60。

公开(公告)号：EP3185290A1

公开(公告)日：2017-06-28

申请号：EP15202661.3

申请日：2015-12-24

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Dubey, Vikas ,  Beyne, Eric ,  Derakhshandeh, Jaber

IPC: H01L23/485 ,  H01L21/60 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/0601 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/8114 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01005 ,  H01L2924/206 ,  H01L2924/20106 ,  H01L2924/207

Abstract: The present disclosure is related to a method for producing a stack of semiconductor devices and the stacked device obtained thereof. The method comprises providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material, providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. Mounting the devices by landing the metal protrusion in the hole, wherein the compliant layer is spaced from the dielectric layer. Thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

Abstract translation: 本公开涉及用于制造半导体器件堆叠的方法以及由此获得的堆叠器件。 该方法包括提供包括具有孔的介电层的第一半导体器件，该孔衬有金属层并且部分地填充有焊料材料，为第二半导体器件提供具有穿过柔性层的金属突起的柔性层，突起 用覆盖层覆盖。 通过将金属突起降落在孔中来安装器件，其中柔性层与介电层间隔开。 此后回流焊料材料，从而键合器件，使得柔性层与介电层接触。

公开(公告)号：EP3151272A1

公开(公告)日：2017-04-05

申请号：EP16189368.0

申请日：2016-09-18

Applicant: Renesas Electronics Corporation

Inventor： TONEGAWA, Takashi

IPC: H01L23/485 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31 ,  H01L21/31056 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/44 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L29/7802 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/031 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03522 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2924/05042 ,  H01L2924/0509 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/1206 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/059 ,  H01L2924/0103 ,  H01L2924/00

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film (PRO1) provided over an interconnection (M1) and having an opening (OA1), and a plating film (OPM1) provided in the opening (OA1). A slit (SL) is provided in a side face of the opening (OA1), and the plating film (OPM1) is also disposed in the slit (SL). Thus, the slit is provided in the side face of the opening (OA1), and the plating film (OPM1) is also grown in the slit (SL). This results in a long penetration path of a plating solution during subsequent formation of the plating film (OPM1). Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit (SL) is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (M1) pad region).

Abstract translation: 半导体器件的性能得到改善。 半导体器件被配置为具有设置在互连（M1）上方且具有开口（OA1）的保护膜（PRO1）以及设置在开口（OA1）中的镀膜（OPM1）。 狭缝（SL）设置在开口（OA1）的侧面中，并且电镀膜（OPM1）也设置在狭缝（SL）中。 因此，在开口部（OA1）的侧面设置狭缝，在狭缝（SL）中也生长镀膜（OPM1）。 这导致在随后形成电镀膜（OPM1）期间电镀溶液的穿透路径较长。 因此，在互连（焊盘区域）中不太可能形成腐蚀部分。 即使形成腐蚀部分，在互连（焊盘区域）之前牺牲部分狭缝（SL）也被腐蚀，使得可以抑制腐蚀部分扩展到互连（M1）焊盘区域）。

公开(公告)号：EP3121843A3

公开(公告)日：2017-04-05

申请号：EP16179960.6

申请日：2016-07-18

Applicant: Semiconductor Components Industries, LLC

Inventor： Seddon, Michael J. ,  Carney, Francis J.

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/98 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A method of flip-chip bonding a plurality of die (10) having at least one metal layer (12) on a die surface to a board (16) comprises placing a first die (10) onto a board (16, 40) comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die (10) and the board (16, 40) into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer (18) and at least one of metal die layers (12) of the first die form an alloy (26) to adhere the first die (10) to the board (16, 40). The newly formed alloy (26) has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and flip-chip attached to the board (16, 40) without causing the bonding of the first die (10) to the board (16) to fail if the same reflow temperature is used and without any metals or alloys connecting (bridging) bond pads of a die (10) or of adjacent die (10).

Abstract translation: 一种将在管芯表面上具有至少一个金属层（12）的多个管芯（10）倒装结合到板（16）的方法，包括：将第一管芯（10）放置到板（16,40）上， 具有可焊表面的陶瓷或基板或金属引线框之一，并将第一管芯（10）和基板（16,40）放入回流炉中。 该方法包括在第一回流温度下回流第一时间段，直到第一管芯的第一金属板层（18）和至少一个金属管芯层（12）形成合金（26）以粘合第一管芯（10 ）到板（16,40）。 新形成的合金（26）具有比第一回流温度更高的熔化温度。 因此，如果使用相同的回流温度并且没有任何金属，则额外的管芯可以回流且倒装连接到板（16,40），而不会导致第一管芯（10）与板（16）的接合失败 或合金连接（桥接）管芯（10）或相邻管芯（10）的接合焊盘。

公开(公告)号：EP3126065A2

公开(公告)日：2017-02-08

申请号：EP15741878.1

申请日：2015-03-31

Applicant: Koninklijke Philips N.V.

Inventor： JACOBS, Egbertus Reinier ,  WEEKAMP, Johannes Wilhelmus ,  RIJKERS, Niels Cornelis Wilhelmus Johannes

IPC: B06B1/02 ,  A61B8/00 ,  H01L23/00 ,  A61B8/12

CPC classification number: B06B1/0292 ,  A61B8/12 ,  A61B8/445 ,  A61B8/4494 ,  H01L21/78 ,  H01L24/01 ,  H01L24/03 ,  H01L24/06 ,  H01L41/0475 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20641 ,  H02N1/006 ,  H05K1/181 ,  H05K2201/10151

Abstract: An integrated circuit (IC) die (100) is disclosed having a major surface delimited by at least one edge (102) of the IC die, said major surface carrying a plurality of electrically conductive contact plates (130) extending from said major surface beyond the at least one edge such that each contact plate includes an exposed contact surface portion (132) delimited by the at least one edge for mating with an electrically conductive further contact surface portion (230) on at least one further edge (220) of a body (200), said at least one further edge delimiting a cavity for receiving the IC die. An ultrasound probe including such an IC die and a method of providing such an IC die with contacts are also disclosed.

Abstract translation: 公开了一种集成电路（IC）管芯（100），其具有由IC管芯的至少一个边缘（102）限定的主表面，所述主表面承载从所述主表面延伸超过的多个导电接触板（130） 所述至少一个边缘使得每个接触板包括由所述至少一个边缘限定的暴露的接触表面部分（132），用于与所述至少一个边缘的至少一个另外的边缘（220）配合的导电的另外的接触表面部分（230） 所述至少一个另外的边缘限定用于容纳IC管芯的空腔。 还公开了一种包括这种IC芯片的超声波探头以及提供具有触点的IC芯片的方法。

公开(公告)号：EP2689455B1

公开(公告)日：2016-08-31

申请号：EP12715748.5

申请日：2012-03-03

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： TOPACIO, Roden, R. ,  SU, Michael, Z. ,  MCLELLAN, Neil

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02233 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.