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公开(公告)号：EP4390926A1
公开(公告)日：2024-06-26
申请号：EP22215794.3
申请日：2022-12-22
申请人： Imec VZW
CPC分类号： G11C7/1006 , G11C11/54 , G06N3/063 , G11C16/26 , G06F7/5443 , G06N3/065
摘要： An in-memory compute device for multiply-and-accumulate operations and methods of operating the same. The device comprises a string of series-connected memory cells (11a-11e) formed over a semiconductor channel structure (12). Each memory cell comprises a programmable threshold transistor to store a weight input. A readout circuit (15) includes a sense node (14) for buffering charge packets transferred from the string of memory cells. Control circuitry is configured for applying pass mode signals, data input signals and stop signals to the control gates of the respective memory cells. Pass mode signals cause memory cells of the string to be switched on, thereby inducing charge packets in the channel structure underneath each memory cell. Data input signals representing binary zeroes and stop signals cause memory cells of the string to be switched off. Data input signals and stop signals are applied sequentially according to each memory cell's position along the string.
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公开(公告)号：EP3506359A1
公开(公告)日：2019-07-03
申请号：EP17211020.7
申请日：2017-12-29
申请人： IMEC vzw
摘要： The disclosed memory device (10) comprises memory elements (11, 12), formed of a stack comprising at least a second magnetic layer (120) over a first magnetic layer (110) arranged on a substrate (100), and selector devices (141, 142) in contact with respective memory elements and arranged in or above the second layer, wherein the memory elements are interconnected via the first layer and separated from each other by a trench (150) formed in the second layer. Preferably, the memory elements are MTJ elements and the selector devices are transistors.
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公开(公告)号：EP3968208A1
公开(公告)日：2022-03-16
申请号：EP20195364.3
申请日：2020-09-09
申请人： Imec VZW
摘要： A compute cell (10) for in-memory multiplication of a digital data input (X) and a balanced ternary weight (w) is disclosed and an in-memory computing device comprising an array thereof. The compute cell comprises a set of input connectors (11a, 11b) for receiving modulated input signals (A+, A-) representative of a sign and a magnitude of the digital data input, and a memory unit (12) configured for storing the balanced ternary weight. A logic unit (13) of the compute cell is connected to the set of input connector and the memory unit (12) to receive the data input and the balanced ternary weight, and is adapted to selectively enable one of a plurality of conductive paths for supplying a partial charge to a read bit line (S; S+, S-) during a compound duty cycle (T) of the set of input signals as a function of the respective signs of data input and ternary weight, and to disable each of the plurality of conductive paths if at least one of the balanced ternary weight and data input have zero magnitude. The compound duty cycle is indicative of the data input magnitude.
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公开(公告)号：EP3923289A1
公开(公告)日：2021-12-15
申请号：EP20179677.8
申请日：2020-06-12
IPC分类号： G11C11/16
摘要： According to an aspect of the present inventive concept there is provided a method for operating a voltage-controlled magnetic anisotropy, VCMA, magnetic tunnel junction, MTJ, device, wherein the MTJ device is switchable between a first resistance state and a second resistance state, and wherein a first threshold voltage for switching the MTJ device from the second resistance state to the first resistance state is lower than a second threshold voltage for switching the MTJ device from the first resistance state to the second resistance state;
the method comprising:
applying a first voltage pulse across the MTJ device with an amplitude having an absolute value equal to or greater than the first threshold voltage and
lower than the second threshold voltage, thereby setting the MTJ device to the first resistance state regardless of whether the MTJ device initially is in the first or second resistance state-
公开(公告)号：EP3888783A1
公开(公告)日：2021-10-06
申请号：EP20167573.3
申请日：2020-04-01
申请人： Imec VZW
摘要： In a first aspect, the present invention relates to a system for addressing nanoelectrodes (30-33) in a nanoelectrode array (20), the system comprising an array of electrode cells (60), each electrode cell (60) comprising: (i) an access transistor (70) having a gate resistively coupled to a word line (71), a source resistively coupled to a bit line (72), and a drain; and (ii) a storage circuit (80) resistively coupled to the drain and comprising a nanoelectrode (30-33).
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公开(公告)号：EP3836384A1
公开(公告)日：2021-06-16
申请号：EP19214763.5
申请日：2019-12-10
申请人： Imec VZW
发明人： COSEMANS, Stefan
摘要： The present invention relates to the field of storage devices configured to store data on a tape. Embodiments of the invention present such a storage device, wherein the storage device comprises the tape, which is configured to store data, the tape including a plurality of first regions with a lower dielectric constant and a plurality of second regions with a higher dielectric constant. The first regions and the second regions are alternatingly arranged along the length of the tape. Further, the storage device comprises one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device comprises one or more data heads configured to read and/or write data from and/or to the tape.
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公开(公告)号：EP3671821A1
公开(公告)日：2020-06-24
申请号：EP18214146.5
申请日：2018-12-19
申请人： IMEC VZW
发明人： COSEMANS, Stefan , RYCKAERT, Julien , TOKEI, Zsolt
IPC分类号： H01L21/768 , H01L23/528
摘要： Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines (20, 21, 22, 23), said multilevel layer comprising at least three levels (L0, L1, L2) forming a centerline level (L1), an upper extension line level (L2) and a lower extension line level (L0) said levels providing multilevel routing tracks in which said lines extend.
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