公开(公告)号：EP4372793A1

公开(公告)日：2024-05-22

申请号：EP22208458.4

申请日：2022-11-21

申请人： IMEC VZW

发明人： GUPTA, Anshul ,  TOKEI, Zsolt ,  DECOSTER, Stefan

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76885 ,  H01L21/76897 ,  H01L23/5283

摘要： The disclosure relates to a method for forming an interconnection structure, comprising:
forming a first dielectric layer pattern over a substrate;
covering the first dielectric layer pattern with metal and planarizing the metal to expose an upper surface of the first dielectric layer pattern and form a first metal layer pattern;
forming a second dielectric layer pattern over the first dielectric layer pattern and the first metal layer pattern;
covering the second dielectric layer pattern with metal and planarizing the metal to expose an upper surface of the second dielectric layer pattern and form a second metal layer pattern;
forming a mask pattern of a mask material over the second dielectric layer pattern and the second metal layer pattern; and
in an etching process comprising using the mask pattern as an etch mask, transferring: a first, second and third sub-pattern of the mask pattern into a first portion of the first metal layer pattern to form a set of lower metal features, a second sub-pattern of the mask pattern into a first portion of the second metal layer pattern and a second portion of the first metal layer pattern to form a set of stacked metal features, and a third sub-pattern of the mask pattern into a second portion of the second metal layer pattern to form a set of upper metal features.

公开(公告)号：EP3671821A1

公开(公告)日：2020-06-24

申请号：EP18214146.5

申请日：2018-12-19

申请人： IMEC VZW

发明人： COSEMANS, Stefan ,  RYCKAERT, Julien ,  TOKEI, Zsolt

IPC分类号： H01L21/768 ,  H01L23/528

摘要： Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines (20, 21, 22, 23), said multilevel layer comprising at least three levels (L0, L1, L2) forming a centerline level (L1), an upper extension line level (L2) and a lower extension line level (L0) said levels providing multilevel routing tracks in which said lines extend.

公开(公告)号：EP3208835A1

公开(公告)日：2017-08-23

申请号：EP16156336.6

申请日：2016-02-18

申请人： IMEC VZW

发明人： BÖMMELS, Jürgen ,  TOKEI, Zsolt ,  WILSON, Chris

IPC分类号： H01L21/768

CPC分类号： H01L21/76813 ,  H01L21/76811 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897

摘要： An interconnect structure (12) comprising:
a. a first entity (1) comprising a first set of two or more conductive lines (2) having coplanar top surfaces (5), the conductive lines (2) being separated by a first set of one or more dielectric lines (3) having coplanar top surfaces (6) positioned above the top surfaces (5) of the conductive lines (2) thereby forming dielectric ridges (4) between the conductive lines (2),
b. a first dielectric etch-stop layer (7a) overlaying the first entity (1), and
c. a low-k dielectric material (8) overlaying the first dielectric etch-stop layer (7a),
wherein a via (9) is formed through the low-k dielectric material (8) and the first dielectric etch stop layer (7a), the via (9) exposing a portion (11) of a conductive line (2), the via (9) being filled with a conductive material (18); and a method for making the same.

摘要翻译： 一种互连结构（12），包括：a。 包括具有共面顶表面（5）的第一组两个或更多个导电线（2）的第一实体（1），所述导电线（2）由具有共面的第一组一个或多个电介质线 定位在导线（2）的顶表面（5）上方的顶表面（6），从而在导线（2），b之间形成介电脊（4）。 覆盖第一实体（1）的第一电介质蚀刻停止层（7a），以及c。 覆盖所述第一介电蚀刻停止层（7a）的低k介电材料（8），其中穿过所述低k介电材料（8）和所述第一介电蚀刻停止层（7a）形成通孔（9） 所述通孔（9）暴露导电线（2）的一部分（11），所述通孔（9）填充有导电材料（18）; 及其制造方法。

公开(公告)号：EP2850653B1

公开(公告)日：2016-03-16

申请号：EP13722750.0

申请日：2013-05-14

申请人： IMEC VZW

发明人： CARBONELL, Laure Elisa ,  PETER, Antony Premkumar ,  SCHAEKERS, Marc ,  VAN ELSHOCHT, Sven ,  TOKEI, Zsolt

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

公开(公告)号：EP2850653A1

公开(公告)日：2015-03-25

申请号：EP13722750.0

申请日：2013-05-14

申请人： IMEC VZW

发明人： CARBONELL, Laure Elisa ,  PETER, Antony Premkumar ,  SCHAEKERS, Marc ,  VAN ELSHOCHT, Sven ,  TOKEI, Zsolt

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

公开(公告)号：EP4362075A1

公开(公告)日：2024-05-01

申请号：EP22203696.4

申请日：2022-10-25

申请人： IMEC VZW

发明人： CHAN, Boon Teik ,  MERTENS, Hans ,  TOKEI, Zsolt ,  HORIGUCHI, Naoto

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC分类号： H01L23/5286 ,  H01L23/535 ,  H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823431

摘要： According to an aspect there is provided a method for interconnecting a buried wiring line and a source/drain body, the method comprising:
forming a fin structure on a substrate, the fin structure comprising at least one channel layer;
forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure;
forming a source/drain body on the at least one channel layer by epitaxy;
forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line;
forming a metal via in the via hole;
forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and
forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby interconnecting the buried wiring line and the source/drain body.

公开(公告)号：EP4199052A1

公开(公告)日：2023-06-21

申请号：EP21215780.4

申请日：2021-12-17

申请人： IMEC VZW

发明人： VEGA GONZALEZ, Victor Hugo ,  CHEHAB, Bilal ,  RYCKAERT, Julien ,  TOKEI, Zsolt ,  BIESEMANS, Serge ,  HORIGUCHI, Naoto

IPC分类号： H01L21/768 ,  H01L21/8238

摘要： A method for forming an integrated circuit comprising the steps of:
a. Providing a semiconductor structure comprising:
i. two transistor structures,
ii. a gate structure,
iii. electrically conductive contacts,
iv. a first electrically conductive line,
v. a first electrically conductive via,
vi. a second electrically conductive via,

b. providing a planar dielectric material in contact with the first electrically conductive line,
c. forming an opening in the planar dielectric material,
d. filling the opening with a planar electrically conductive material,
e. forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material,
f. Providing a hard mask comprising a set of parallel lines,
g. etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

公开(公告)号：EP4050644A1

公开(公告)日：2022-08-31

申请号：EP21158858.7

申请日：2021-02-24

申请人： Imec VZW

发明人： O´TOOLE, Martin ,  MURDOCH, Gayle ,  WECKX, Pieter ,  TOKEI, Zsolt ,  RYCKAERT, Julien

IPC分类号： H01L21/768

摘要： The disclosure relates to a method for forming an interconnect structure, the method comprising:
depositing a conductive layer stack comprising a first and a second conductive layer of different materials, the first conductive layer formed on top of the second conductive layer;
etching a pattern of conductive lines in the conductive layer stack;
forming a via pillar mask on top of a conductive line of said conductive lines; and
etching back the conductive lines using the via pillar mask as an etch mask and the second conductive layer as an etch stop layer, thereby forming underneath the via pillar mask a conductive via pillar in the first conductive layer, the conductive via pillar protruding above etched-back conductive lines.

公开(公告)号：EP3836198A1

公开(公告)日：2021-06-16

申请号：EP19215615.6

申请日：2019-12-12

申请人： Imec VZW

发明人： O´TOOLE, Martin ,  WILSON, Christopher ,  TOKEI, Zsolt ,  KIM, Ryan Ryoung han

IPC分类号： H01L21/768

摘要： According to an aspect of the present inventive concept there is provided a method for forming a via hole (200) self-aligned with a metal block (190) on an interlayer dielectric layer (110) of a substrate, the method (300) comprising: forming a metal comprising layer (120) and a dielectric layer (130) on the interlayer dielectric layer (110), forming a plurality of parallel spacer line structures (140) comprising sidewall oxide layers (150) on the dielectric layer (130) such that a portion of the dielectric layer (130) is exposed between adjacent sidewall oxide layers (150), forming a first sacrificial layer (160), forming an opening in the first sacrificial layer (160) to expose a first portion of the dielectric layer (130), etching through the first portion of the dielectric layer (130), removing the first sacrificial layer (160), forming a second sacrificial layer (160), forming an opening in the second sacrificial layer (160), the opening partially overlapping the opening of the dielectric layer (130) and exposing a second portion of the metal comprising layer (120), selectively depositing a metal block (190) on the exposed second portion of the metal comprising layer (120), removing the second sacrificial layer (160), and etching through the remaining portion of the first portion of the metal comprising layer (120) and the interlayer dielectric layer (110).

公开(公告)号：EP3770953A1

公开(公告)日：2021-01-27

申请号：EP19187767.9

申请日：2019-07-23

申请人： Imec VZW

发明人： BRIGGS, Basoene ,  MACHKAOUTSAN, Vladimir ,  TOKEI, Zsolt

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

摘要： According to an aspect of the present inventive concept there is provided a method for forming a multi-level interconnect structure in a semiconductor device comprising: a first interconnection level (110) including a first dielectric layer (112) and a first conductive structure (114); a second interconnection level (120) arranged above the first interconnection level (110) and including a second dielectric layer (122) and a second conductive structure (124); a third interconnection level (130) arranged above the second interconnection level (120) and including a third dielectric layer (132) and a third conductive structure (134); wherein the method comprises: forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first sacrificial material; removing the second sacrificial material; depositing a conductive material at least partially filling: the trench, thereby forming the third conductive structure (134); the via, thereby forming a via structure (102) forming an electrical connection between the third conductive structure (134) and the second conductive structure (124); and the multi-level via, thereby forming a multi-level via structure (104) forming an electrical connection between the third conductive structure (134) and the first conductive structure (114).