公开(公告)号：EP1419433A2

公开(公告)日：2004-05-19

申请号：EP02753502.0

申请日：2002-08-20

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： DUH, Jiann-Jeng ,  AU, Mario, Fulam

IPC: G06F5/06

CPC classification number: G06F5/06 ,  G06F2205/062

Abstract: First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation circuitry and retransmit circuitry are also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.