公开(公告)号：EP0312239B1

公开(公告)日：1996-05-08

申请号：EP88309253.8

申请日：1988-10-05

Applicant: NORTHERN TELECOM LIMITED

Inventor： Lefebvre, Martin Claude ,  Ciancibello, Carmine Antonio ,  Geadah, Youssef Alfred

IPC: G06F5/06

CPC classification number: G06F5/14 ,  G06F2205/062

公开(公告)号：EP0312239A3

公开(公告)日：1991-02-13

申请号：EP88309253.8

申请日：1988-10-05

Applicant: NORTHERN TELECOM LIMITED

Inventor： Lefebvre, Martin Claude ,  Ciancibello, Carmine Antonio ,  Geadah, Youssef Alfred

IPC: G06F5/06

CPC classification number: G06F5/14 ,  G06F2205/062

Abstract: A FIFO (first in first out) control circuit (211) for providing address information to a FIFO memory (212). Two up counters (217, 218) are used; one to provide the write address and one to provide the read address. A multiplexer (219) selects which addresses (read or write) are used. Two storage registers (243,244) are used to temporarily "hold" the output from the counters. This enables the counters to be re-loaded with their original "count" to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Logic circuitry is used to provide two status output signals, name full (or not) and empty (or not).

公开(公告)号：EP2045973A1

公开(公告)日：2009-04-08

申请号：EP07117776.0

申请日：2007-10-02

Applicant: Deutsche Thomson OHG

Inventor： Siemens, Eduard ,  Qiu, Xiaopeng

IPC: H04L12/56 ,  H04L1/18 ,  G06F5/12

CPC classification number: H04L1/1874 ,  G06F5/12 ,  G06F2205/062 ,  H04L1/1835 ,  H04L47/6245 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9047

Abstract: This invention relates to a design of an efficient buffer management model in order to increase the efficiency of data exchange between two process threads, - e.g. when implementing a network transport protocol stack.
This invention proposes to use an interconnected system of different kinds of memory buffers (100, 101, 102), implemented as asynchronous read/write ring buffers ARWRB. These buffers are organized in a way, in which data can be stored into the buffer or fetched from the buffer essentially avoiding synchronization means like mutexes or semaphores.
In contrast to the conventional buffer management model, three ring buffers, namely send ring buffer (100), send token ring buffer (101) and receive ring buffer (102), are used within the transport protocol stack.

Abstract translation: 本发明涉及一种高效的缓存器管理模型的设计，以增加两个处理线程之间的数据交换的效率 - E. G. 当实现一个网络传输协议栈。 本发明提出了作为异步读/写环形缓冲器ARWRB在不同种类的存储器缓冲器（100，101，102），来实现的互连的系统中使用。 这些缓冲器的方式，在该数据可被存储到从基本上避免同步缓存器中的缓冲或取出组织等手段或互斥信号量。 与此相反的常规缓冲器管理模式，三个环形缓冲器，即发送环形缓冲器（100），发送令牌环缓冲器（101）和接收环形缓冲区（102）的传送协议栈内被使用。

公开(公告)号：EP1962181A1

公开(公告)日：2008-08-27

申请号：EP06833543.9

申请日：2006-11-28

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： FUJIBAYASHI, Masanori, c/o Matsushita Electric Industrial Co.,Ltd., IPROC, 7F Twin 21 OBP ,  HIGAKI, Nobuo, c/o Matsushita Electric Industrial Co., Ltd., IPROC, 7F Twin 21 OBP ,  KURATA, Kazushi, c/o Matsushita Electric Industrial Co., Ltd., IPROC, 7F Twin 21 OBP ,  MATSUI, Tomoko, c/o Matsushita Electric Industrial Co., Ltd., IPROC,7F Twin 21 OBP

IPC: G06F5/06 ,  G06F12/02

CPC classification number: G06F5/14 ,  G06F2205/062

Abstract: The buffer control device of this invention includes: a pointer holding unit (102, 103) which holds a virtual pointer different from a read pointer and a write pointer; an access control unit (106, 111) that controls an access to a ring buffer; a judging unit (104 a/b, 109 a/b) that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and stop flags Sr and Sw that disable a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit (106, 111) further controls a reaccess to the ring buffer.

Abstract translation: 本发明的缓冲器控制装置包括：保持与读指针不同的虚拟指针和写指针的指针保持单元（102,103）; 控制对环形缓冲器的访问的访问控制单元（106,111）; 判断单元（104a / b，109a / b），其判断所述读指针和写指针中的一个是否已经达到与所述虚拟指针所指示的地址基本相同的地址; 并且当判断单元判断读取指针和写入指针中的一个已经达到与所指示的地址基本相同的地址时，使用读取指针和写入指针中的一个禁止正常访问的停止标志Sr和Sw 虚拟指针，正常访问由访问控制单元控制，其中访问控制单元（106,111）还控制对环形缓冲器的重新访问。

公开(公告)号：EP0425964A2

公开(公告)日：1991-05-08

申请号：EP90120229.1

申请日：1990-10-22

Applicant: MOTOROLA, INC.

Inventor： Bedlek, Gregory J. ,  White, Richard E. ,  Freeburg, Thomas A.

IPC: H04J3/06

CPC classification number: G06F5/10 ,  G06F2205/062 ,  G06F2205/104 ,  H04J3/0626 ,  H04L25/05

Abstract: A method and means of performing the asynchronous reconstruction of a digital data stream is disclosed. An input data stream having an input rate, such as digitized speech, is stored in a circular buffer (250). Within the buffer (250), read and write marker positions (300 and 301) are determined. Upon subsequent retrieval of the data stream at an output rate, data is taken from the position of the read marker (301) each time data is written to the position of the write marker (300). Of importance, the read and write marker positions (300 and 301) are determined such that they provide a delay (A) greater than the difference between the input rate and the output rate over the length of the buffer (250). The data stream processing is then modified by ignoring at least some of the data stream when the input rate is faster than the output rate, and repeating at least some of the data stream when the input rate is slower than the output rate. In this manner a method of digitized voice reconstruction without reliance upon network synchronization is achieved.

Abstract translation: 公开了一种执行数字数据流的异步重构的方法和装置。 具有诸如数字化语音的输入速率的输入数据流被存储在循环缓冲器（250）中。 在缓冲器（250）内，确定读写标记位置（300和301）。 在以输出速率随后检索数据流时，每当将数据写入写标记（300）的位置时，从读标记（301）的位置取数据。 重要的是，读取和写入标记位置（300和301）被确定为使得它们提供比在缓冲器（250）的长度上的输入速率和输出速率之间的差大的延迟（A）。 然后当输入速率比输出速率快时，通过忽略至少一些数据流来修改数据流处理，并且当输入速率比输出速率慢时重复数据流中的至少一些。 以这种方式，实现了不依赖于网络同步的数字化语音重构的方法。

公开(公告)号：EP2206294B1

公开(公告)日：2018-05-16

申请号：EP08804222.1

申请日：2008-09-15

Applicant: Tixel GmbH

Inventor： SIEMENS, Eduard ,  QIU, Xiaopeng

IPC: H04L12/54 ,  H04L12/863 ,  H04L12/861 ,  H04L12/879 ,  H04L1/18 ,  G06F5/12

CPC classification number: H04L1/1874 ,  G06F5/12 ,  G06F2205/062 ,  H04L1/1835 ,  H04L47/6245 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9047

Abstract: This invention relates to a design of an efficient buffer management model in order to increase the efficiency of data exchange between two process threads, - e.g. when implementing a network transport protocol stack. This invention proposes to use an interconnected system of different kinds of memory buffers (100, 101, 102), implemented as asynchronous read/write ring buffers ARWRB. These buffers are organized in a way, in which data can be stored into the buffer or fetched from the buffer essentially avoiding synchronization means like mutexes or semaphores. In contrast to the conventional buffer management model, three ring buffers, namely send ring buffer (100), send token ring buffer (101) and receive ring buffer (102), are used within the transport protocol stack.

公开(公告)号：EP1962181A4

公开(公告)日：2010-05-26

申请号：EP06833543

申请日：2006-11-28

Applicant: PANASONIC CORP

Inventor： FUJIBAYASHI MASANORI ,  HIGAKI NOBUO ,  KURATA KAZUSHI ,  MATSUI TOMOKO

IPC: G06F5/06 ,  G06F5/14 ,  G06F12/02

CPC classification number: G06F5/14 ,  G06F2205/062

公开(公告)号：EP0312239A2

公开(公告)日：1989-04-19

申请号：EP88309253.8

申请日：1988-10-05

Applicant: NORTHERN TELECOM LIMITED

Inventor： Lefebvre, Martin Claude ,  Ciancibello, Carmine Antonio ,  Geadah, Youssef Alfred

IPC: G06F5/06

CPC classification number: G06F5/14 ,  G06F2205/062

Abstract: A FIFO (first in first out) control circuit (211) for providing address information to a FIFO memory (212). Two up counters (217, 218) are used; one to provide the write address and one to provide the read address. A multiplexer (219) selects which addresses (read or write) are used. Two storage registers (243,244) are used to temporarily "hold" the output from the counters. This enables the counters to be re-loaded with their original "count" to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Logic circuitry is used to provide two status output signals, name full (or not) and empty (or not).

Abstract translation: 一种用于向FIFO存储器（212）提供地址信息的FIFO（先进先出）控制电路（211）。 使用两个向上计数器（217,218）; 一个提供写地址，一个提供读地址。 多路复用器（219）选择使用哪个地址（读或写）。 两个存储寄存器（243,244）用于临时“保持”计数器的输出。 这使得计数器能够重新加载其原始的“计数”，以便能够重新读取或重新写入存储在FIFO存储器中的消息。 逻辑电路用于提供两个状态输出信号，名称满（或不）和空（或不）。

公开(公告)号：EP2206294A1

公开(公告)日：2010-07-14

申请号：EP08804222.1

申请日：2008-09-15

Applicant: Thomson Licensing

Inventor： SIEMENS, EDUARD ,  QIU, XIAOPENG

IPC: H04L12/56 ,  H04L1/18 ,  G06F5/12

CPC classification number: H04L1/1874 ,  G06F5/12 ,  G06F2205/062 ,  H04L1/1835 ,  H04L47/6245 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9047

Abstract: This invention relates to a design of an efficient buffer management model in order to increase the efficiency of data exchange between two process threads, - e.g. when implementing a network transport protocol stack. This invention proposes to use an interconnected system of different kinds of memory buffers (100, 101, 102), implemented as asynchronous read/write ring buffers ARWRB. These buffers are organized in a way, in which data can be stored into the buffer or fetched from the buffer essentially avoiding synchronization means like mutexes or semaphores. In contrast to the conventional buffer management model, three ring buffers, namely send ring buffer (100), send token ring buffer (101) and receive ring buffer (102), are used within the transport protocol stack.

Abstract translation: 本发明涉及一种高效的缓存器管理模型的设计，以增加两个处理线程之间的数据交换的效率 - E. G. 当实现一个网络传输协议栈。 本发明提出了作为异步读/写环形缓冲器ARWRB在不同种类的存储器缓冲器（100，101，102），来实现的互连的系统中使用。 这些缓冲器的方式，在该数据可被存储到从基本上避免同步缓存器中的缓冲或取出组织等手段或互斥信号量。 与此相反的常规缓冲器管理模式，三个环形缓冲器，即发送环形缓冲器（100），发送令牌环缓冲器（101）和接收环形缓冲区（102）的传送协议栈内被使用。

公开(公告)号：EP1419433A2

公开(公告)日：2004-05-19

申请号：EP02753502.0

申请日：2002-08-20

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： DUH, Jiann-Jeng ,  AU, Mario, Fulam

IPC: G06F5/06

CPC classification number: G06F5/06 ,  G06F2205/062

Abstract: First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation circuitry and retransmit circuitry are also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.