公开(公告)号：EP1649653A1

公开(公告)日：2006-04-26

申请号：EP04756759.9

申请日：2004-07-08

申请人： INTEL CORPORATION

发明人： GRIFFIN, Jed ,  JEX, Jerry ,  FORESTIER, Arnaud ,  VAKIL, Kersi ,  KOLLA, Abhimanyu

IPC分类号： H04L27/24

CPC分类号： H04L25/4904 ,  H04L25/0272 ,  H04L27/24

摘要： In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal. Still other embodiments are described and claimed.

公开(公告)号：EP1994472A1

公开(公告)日：2008-11-26

申请号：EP07758469.6

申请日：2007-03-13

申请人： Intel Corporation

发明人： VAKIL, Kersi ,  KOLLA, Abhimanyu

IPC分类号： G06F13/20 ,  G06F13/16 ,  G06F13/00

CPC分类号： G06F13/4256 ,  G06F13/1684

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for an input/output agent having multiple secondary ports. In some embodiments, the input/output agent includes a primary port to communicate data with an upstream agent over a serial point-to-point interconnect. The input/output agent may also include M secondary ports to communicate data with a corresponding M downstream agents, wherein downstream data is forwarded from the primary port to at least one of the M secondary ports.

公开(公告)号：EP1647119B1

公开(公告)日：2012-06-13

申请号：EP04777713.1

申请日：2004-07-08

申请人： Intel Corporation

发明人： GRIFFIN, Jed c/o Intel Corporation ,  JEX, Jerry ,  FORESTIER, Arnaud ,  VAKIL, Kersi ,  KOLLA, Abhimanyu

IPC分类号： H04L27/24 ,  H04L25/49 ,  H04L1/06 ,  H04L7/00

CPC分类号： H04L27/24 ,  H04L1/06 ,  H04L25/4904

摘要： In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.

公开(公告)号：EP1649653B1

公开(公告)日：2011-07-20

申请号：EP04756759.9

申请日：2004-07-08

申请人： Intel Corporation

发明人： GRIFFIN, Jed ,  JEX, Jerry ,  FORESTIER, Arnaud ,  VAKIL, Kersi ,  KOLLA, Abhimanyu

IPC分类号： H04L27/24

CPC分类号： H04L25/4904 ,  H04L25/0272 ,  H04L27/24

摘要： In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal. Still other embodiments are described and claimed.

公开(公告)号：EP1647119A2

公开(公告)日：2006-04-19

申请号：EP04777713.1

申请日：2004-07-08

申请人： INTEL CORPORATION

发明人： GRIFFIN, Jed ,  JEX, Jerry ,  FORESTIER, Arnaud ,  VAKIL, Kersi ,  KOLLA, Abhimanyu

IPC分类号： H04L27/24 ,  H04L25/49 ,  H04L1/06 ,  H04L7/00

CPC分类号： H04L27/24 ,  H04L1/06 ,  H04L25/4904

摘要： In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.