公开(公告)号：EP3716102A1

公开(公告)日：2020-09-30

申请号：EP20159725.9

申请日：2020-02-27

申请人： Intel Corporation

发明人： AZIZI, Omid

IPC分类号： G06F17/16

摘要： This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

公开(公告)号：EP3588306A1

公开(公告)日：2020-01-01

申请号：EP19175771.5

申请日：2019-05-21

申请人： INTEL Corporation

发明人： FIROOZSHAHIAN, Amin ,  AZIZI, Omid ,  EGBERT, Chandan ,  HANSEN, David ,  KLEEN, Andreas ,  MADDURY, Mahesh ,  MADHAV, Mahesh ,  SOLOMATNIKOV, Alexandre ,  STEVENSON, Peter

IPC分类号： G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/126 ,  G06F12/128 ,  G06F12/0895 ,  G06F12/0871

摘要： Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

公开(公告)号：EP3547150B1

公开(公告)日：2020-11-04

申请号：EP19159850.7

申请日：2019-02-27

申请人： INTEL Corporation

发明人： FIROOZSHAHIAN, Amin ,  GEETHA, Vedaraman ,  KLEEN, Andreas ,  VAN DOREN, Stephen ,  AZIZI, Omid ,  MADHAV, Mahesh ,  MADDURY, Mahesh ,  EGBERT, Chandan

IPC分类号： G06F13/16 ,  G06F9/50 ,  G06F11/30 ,  G06F3/06 ,  H04L12/825 ,  H04L12/801 ,  H04L12/26 ,  G06F11/07 ,  G06F11/34 ,  H04L12/815 ,  H04L12/841

公开(公告)号：EP3547150A1

公开(公告)日：2019-10-02

申请号：EP19159850.7

申请日：2019-02-27

申请人： INTEL Corporation

发明人： FIROOZSHAHIAN, Amin ,  GEETHA, Vedaraman ,  KLEEN, Andreas ,  VAN DOREN, Stephen ,  AZIZI, Omid ,  MADHAV, Mahesh ,  MADDURY, Mahesh ,  EGBERT, Chandan

IPC分类号： G06F13/16 ,  H04L12/825 ,  G06F3/06 ,  H04L12/801 ,  G06F11/30 ,  H04L12/26 ,  G06F9/50 ,  H04L12/811 ,  H04L12/835

摘要： Various systems and methods for controlling memory traffic flow rate are described herein. A system (300A) for computer memory (306A, 306B) management, the system comprising: rate control circuitry (312) to: receive a rate exceeded signal from monitoring circuitry (310), the rate exceeded signal indicating that memory traffic flow from a traffic source (302) exceeds a threshold; receive a distress signal from a memory controller (304) that interfaces with a memory device (306A, 306B), the distress signal indicating that the memory device (306A, 306B) is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source (302) when the rate exceeded signal and the distress signal are both asserted.