公开(公告)号：EP3588306A1

公开(公告)日：2020-01-01

申请号：EP19175771.5

申请日：2019-05-21

申请人： INTEL Corporation

发明人： FIROOZSHAHIAN, Amin ,  AZIZI, Omid ,  EGBERT, Chandan ,  HANSEN, David ,  KLEEN, Andreas ,  MADDURY, Mahesh ,  MADHAV, Mahesh ,  SOLOMATNIKOV, Alexandre ,  STEVENSON, Peter

IPC分类号： G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/126 ,  G06F12/128 ,  G06F12/0895 ,  G06F12/0871

摘要： Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.