利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.019 秒)

    LOW POWER ENTRY IN A SHARED MEMORY LINK
    2.
    发明授权
    LOW POWER ENTRY IN A SHARED MEMORY LINK 有权
    低功率输入共享内存链接

    公开(公告)号：EP3035198B1

    公开(公告)日：2017-08-23

    申请号：EP15194805.6

    申请日：2015-11-16

    申请人： Intel Corporation

    发明人： JEN, Michelle C. ,  SHARMA, Debendra Das ,  WAGH, Mahesh ,  IYER, Venkatraman

    IPC分类号： G06F13/38 ,  G06F1/32

    CPC分类号： G06F3/0625 ,  G06F1/3234 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/385

    摘要： Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.

    摘要翻译： 根据存储器访问链路协议，数据被发送以对应于与链路上的共享存储器相关联的加载/存储类型操作，并且存储器访问链路协议将被覆盖在另一个不同的链路协议上。 发送请求以进入低功率状态，其中请求包括编码在令牌的字段中的数据值，该令牌用于指示分组数据的开始，并且进一步指示后续数据是否在发送之后被发送 该令牌将包括根据其他链路协议和存储器访问链路协议之一的数据。

    A METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT
    3.
    发明公开
    A METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT 审中-公开
    VERFAHREN，VORRICHTUNG UND SYSTEM ZUR LATENZMESSUNG IN EINER PHYSIKALISCHEN EINHEIT EINER SCHALTUNG

    公开(公告)号：EP3063640A1

    公开(公告)日：2016-09-07

    申请号：EP13896809.4

    申请日：2013-10-30

    申请人： Intel Corporation

    发明人： HARRIMAN, David J. ,  WAGH, Mahesh ,  ISMAIL, Abdul R. ,  FROELICH, Daniel S.

    IPC分类号： G06F13/00 ,  G06F1/04

    摘要： In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，一种装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的反射镜弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，以及确定转接 数据元素至少部分地基于计数器输出样本和当前计数器值来遍历接收机电路的等待时间。 描述和要求保护其他实施例。

    PROVIDING A LOAD/STORE COMMUNICATION PROTOCOL WITH A LOW POWER PHYSICAL UNIT
    8.
    发明公开
    PROVIDING A LOAD/STORE COMMUNICATION PROTOCOL WITH A LOW POWER PHYSICAL UNIT 审中-公开
    提供充电/存储装置的通信协议与物理低功率版本

    公开(公告)号：EP3133796A1

    公开(公告)日：2017-02-22

    申请号：EP16191580.6

    申请日：2013-05-16

    申请人： Intel Corporation

    发明人： WAGH, Mahesh ,  RANGANATHAN, Sridharan ,  HARRIMAN, David

    IPC分类号： H04L29/10 ,  H04L29/06 ,  G06F13/40 ,  G06F13/38 ,  H04L12/933

    CPC分类号： G06F13/385 ,  G06F13/40 ,  H04L49/109

    摘要： In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    摘要翻译： 在一个，实施例会聚协议栈可用于统一从第一通信协议通信的第二通信协议来提供用于跨物理互连的数据传送。 这种叠层可以被结合到装置确实包括用于第一通信协议包括事务层和链路层的协议栈，以及耦合到所述协议栈中的物理（PHY）单元，以提供装置和经由耦合到所述设备的装置之间的通信 物理链路。 这个PHY单元可以包括物理单元电路gemäß到所述第二通信协议。 其他实施例中描述并要求保护。

    PROVIDING A LOAD/STORE COMMUNICATION PROTOCOL WITH A LOW POWER PHYSICAL UNIT
    9.
    发明公开
    PROVIDING A LOAD/STORE COMMUNICATION PROTOCOL WITH A LOW POWER PHYSICAL UNIT 审中-公开
    提供低功耗物理单元的加载/存储通信协议

    公开(公告)号：EP2853079A1

    公开(公告)日：2015-04-01

    申请号：EP13793792.6

    申请日：2013-05-16

    申请人： Intel Corporation

    发明人： RANGANATHAN, Sridharan ,  WAGH, Mahesh ,  HARRIMAN, David J.

    IPC分类号： H04L29/10 ,  H04L29/06

    CPC分类号： G06F13/385 ,  G06F13/40 ,  H04L49/109

    摘要： In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供通过物理互连的数据传输。 该堆栈可以被包含在包括用于包括事务和链路层的第一通信协议的协议栈和耦合到协议栈以提供设备与耦合到该装置的设备之间的通信的物理（PHY）单元的设备中 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述并要求保护其他实施例。

    A METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT
    10.
    发明公开
    A METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT 审中-公开

    公开(公告)号：EP4254209A3

    公开(公告)日：2023-11-22

    申请号：EP23193275.7

    申请日：2013-10-30

    申请人： INTEL Corporation

    发明人： HARRIMAN, David J. ,  WAGH, Mahesh ,  ISMAIL, Abdul R. ,  FROELICH, Daniel S.

    IPC分类号： G06F13/38

    摘要： In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.