公开(公告)号：EP4149008A1

公开(公告)日：2023-03-15

申请号：EP22188197.2

申请日：2022-08-02

申请人： INTEL Corporation

发明人： Gopal, Vinodh ,  Guilford, James D. ,  Cutter, Daniel F.

IPC分类号： H03M7/30 ,  G06F11/10 ,  H03M7/40

摘要： Methods and apparatus relating to verifying a compressed stream fused with copy or transform operation(s) are described. In an embodiment, compression logic circuitry compresses input data and stores the compressed data in a temporary buffer. The compression logic circuitry determines a first checksum value corresponding to the compressed data stored in the temporary buffer. Decompression logic circuitry performs a decompress-verify operation and a copy operation. The decompress-verify operation decompresses the compressed data stored in the temporary buffer to determine a second checksum value corresponding to the decompressed data from the temporary buffer. The copy operation transfers the compressed data from the temporary buffer to a destination buffer in response to a match between the first checksum value and the second checksum value. Other embodiments are also disclosed and claimed.