公开(公告)号：EP3584837A1

公开(公告)日：2019-12-25

申请号：EP19173106.6

申请日：2019-05-07

申请人： INTEL Corporation

发明人： HASNAT, Khaled ,  MAJHI, Prashant

IPC分类号： H01L27/11548 ,  H01L27/11595 ,  H01L27/11556 ,  H01L21/20 ,  H01L27/11526 ,  H01L21/18

摘要： Three-dimensional (3D) memory with control the array and control circuitry in separately processed and bonded wafers is described. In one example, a non-volatile storage component includes a first die including a three-dimensional (3D) array of non-volatile storage cells and a second die bonded with the first die. The second die includes CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells. By processing the CMOS circuitry and array on separate wafers, the periphery CMOS and interconnects do not have to withstand the thermal cycles involved in processing the memory array, which enables optimizations for the CMOS transistors and the use low resistive material for interconnects.