公开(公告)号：EP3945583A1

公开(公告)日：2022-02-02

申请号：EP21188312.9

申请日：2021-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： YANG, TsuChing ,  SUN, Hung-Chang ,  LAI, Sheng-Chih ,  JIANG, Yu-Wei ,  CHIANG, Kuo-Chang

IPC分类号： H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11587 ,  H01L27/11595 ,  H01L27/11597

摘要： A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.

公开(公告)号：EP4102504A1

公开(公告)日：2022-12-14

申请号：EP22164365.3

申请日：2022-03-25

申请人： Intel Corporation

发明人： RAHMAN, Ahsanur ,  GULARTE, Richard M. ,  KOH, Hoon ,  HA, Chang Wan ,  MEYAARD, David ,  LIU, Liu ,  THIMMEGOWDA, Deepak

IPC分类号： G11C5/02 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11595

摘要： An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

公开(公告)号：EP3584837A1

公开(公告)日：2019-12-25

申请号：EP19173106.6

申请日：2019-05-07

申请人： INTEL Corporation

发明人： HASNAT, Khaled ,  MAJHI, Prashant

IPC分类号： H01L27/11548 ,  H01L27/11595 ,  H01L27/11556 ,  H01L21/20 ,  H01L27/11526 ,  H01L21/18

摘要： Three-dimensional (3D) memory with control the array and control circuitry in separately processed and bonded wafers is described. In one example, a non-volatile storage component includes a first die including a three-dimensional (3D) array of non-volatile storage cells and a second die bonded with the first die. The second die includes CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells. By processing the CMOS circuitry and array on separate wafers, the periphery CMOS and interconnects do not have to withstand the thermal cycles involved in processing the memory array, which enables optimizations for the CMOS transistors and the use low resistive material for interconnects.

公开(公告)号：EP3944321A1

公开(公告)日：2022-01-26

申请号：EP21186919.3

申请日：2021-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： LIN, Meng-Han ,  CHIA, Han-Jong ,  LIU, Yi-Ching ,  HUANG, Chia-En ,  WANG, Sheng-Chen ,  YANG, Feng-Cheng ,  LIN, Chung-Te

IPC分类号： H01L27/11587 ,  H01L27/11595 ,  H01L27/11597

摘要： A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device include a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

公开(公告)号：EP3440700A1

公开(公告)日：2019-02-13

申请号：EP17776028.7

申请日：2017-01-11

申请人： Intel Corporation

发明人： THIMMEGOWDA, Deepak ,  YIP, Aaron ,  HELM, Mark ,  LI, Yongna

IPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11597 ,  H01L27/11595 ,  H01L27/24